This paper presents a method for the generation of controller specifications from high-level behavioral descriptions in control and timing graph form. Input descriptions may contain multiple timing constraints, asynchronous and synchronous inputs, data dependent internal loops, and parallel and conditional branches. The timing graph model is transformed automatically to a state table specification of a synchronous finite state machine. The specification method is effective not only for independent data processors, but also for processors constrained by interface requirements and performing I/O protocol translation. The method has been programmed and tested on selected examples. Results from one example are given along with a comparison with results on the same example from another system.

The authors describe a formalism for the representation of interface behavior which can be used for high-level synthesis by a design automation system. The Design Data Structure can represent the many facets of interface behavior in a unified way, including timing constraints, synchronous and asynchronous signals, control flow, and data manipulation. Its descriptive power is more complete than some other formalisms in use, including event and annotated data-flow graphs. The representations described here can be used by data path synthesizers to capture more complex timing information than is typically handled and to separate control from data manipulation information to produce cleaner data flow graphs. The Design Data Structure has been used successfully as an internal representation for a natural-language interface for system specification.>

This paper describes the automatic design of custom integrated circuits from higher level specifications. The paper covers four topic areas: the problem domain and solution approach, higher level synthesis, module to layout automation systems, typically called silicon compiliers, and expert systems which control the design process. In the first three sections, several features of the VLSI problem domain which complicate automation are listed. The VLSI design process is diagrammed and the individual steps described. The term "silicon compilation" is defined to cover the entire process, and definitions for various subcategories of silicon compilers are given. The next Section describes both algorithmic and knowledge-based techniques Which perform higher level synthesis, including area estimation and module binding concurrent with synthesis. Research at Bell Labs, USC, CMU, and in Canada is described, along with other projects. The fifth section discusses the three categories of silicon compilers: commercially available systems, experimental compilers being developed by industry, and artificial intelligence approaches from university research. A survey of several systems is provided. The last section focuses on two systems developed at CMU and USC which plan or control design activities, Ulysses and DPE. Both systems allow the integration of various design automation tools and determine the proper tool invocation to automatically create a design. ADAM takes an autonomous approach, while ULYSSES follows user-defined scripts.