A local constrained multiobjective Bayesian optimization (LoCoMOBO) method is introduced to address automatic sizing and tradeoff exploration for analog and RF integrated circuits (ICs). LoCoMOBO applies to constrained optimization problems utilizing multiple Gaussian process (GP) models that approximate the objective and constraint functions locally in the search space. It searches for potential pareto optimal solutions within trust regions of the search space using only a few time-consuming simulations. The trust regions are adaptively updated during the optimization process based on feasibility and hypervolume metrics. In contrast to mainstream Bayesian optimization approaches, LoCoMOBO uses a new acquisition function that can provide multiple query points, therefore allowing for parallel execution of costly simulations. GP inference is also enhanced by using GPU acceleration in order to handle highly constrained problems that require large sample budgets. Combined with a framework for schematic parametrization and simulator calls, LoCoMOBO provides improved performance tradeoffs and sizing results on three real-world circuit examples, while reducing the total runtime up to$\times 43$times compared to state-of-the-art methods.

This paper proposes a Bayesian Optimization (BO) algorithm to handle large-scale analog circuit sizing. The proposed approach uses a number of separate Gaussian Process (GP) models approximating the objective and constraint functions locally in the search space. Unlike mainstream BO approaches, it is able to traverse high dimensional problems with ease and provide multiple query points for parallel evaluation. To extend the method to large sample budgets, GP regression and sampling are enhanced by using kernel approximations and GPU acceleration. Experimental results demonstrate that the proposed method finds better solutions within given budgets of total evaluations compared to state-of-the-art approaches.