This work investigates proposed maximum-powerpoint tracking (MPPT) approaches for a fully integrated hybrid voltage converter (H-VC) intended for alternative energy sources in low-power Internet of Things (IoT) systems, where passive components and power supply rail stability impose severe constraints. A monolithic Hybrid-Dual-Path (HDPC) voltage converter with an on-chip$L_{\text{DC}}=15.07 n H$inductor and strongly limited total capacitance ($C_{\text{IN}}=C_{\text{OUT}} \approx 2.5 n F$) is considered, with 1.5 V output voltage regulation provided by a continuously operating shunt-type regulator. The two MPPT concepts are analyzed: (i) iMPPT based on the fractional open-circuit-voltage (FOCV) principle, which is energy-efficient but requires periodic$V_{\text{IN,OC}}$sampling via short-time disconnection of alternative energy sources (AES), and (ii) oMPPT, which maximizes extracted load power by optimizing the combined product$\eta_{\text{MPPT}}.\eta_{\text{VC}}$and provides instantaneous power observability in a form of digital code. The feasibility and performance are evaluated in Cadence using a TSMC 65 nm CMOS technology and a realistic PV model (KXOB25-14X1F), across irradiance levels of 5-500 W/m2corresponding to PIN,MPPfrom$114 \mu W$to 14.8 mW. Simulation results show that both approaches regulate operation over a wide switching-frequency span of roughly 0.9-62 MHz via FrequencyShift Modulation Control (FSM-C). Overall, iMPPT is favored when minimal control overhead is paramount, whereas oMPPT offers superior scalability and algorithmic flexibility for broader AES applicability at the cost of up to 5.5 times higher power consumption.

This work presents the 1.2 V Low-Dropout Regulator (LDO) designed in a standard 65 nm CMOS technology using data obtained from experimental verification of 9 prototype chips. The measurement of standard parameters that were evaluated included Load Regulation (LDR) in the output current I out range from$\mathbf{1} \boldsymbol{\mu} \mathbf{A}$to$\mathbf{3 0 0} \boldsymbol{\mu} \mathbf{A}$, Line Regulation (LNR) at$\boldsymbol{I}_{\text {out }}$of$100 \mu ~\mathrm{A}$and$300 \mu ~\mathrm{A}$, Drop-Out voltage and PSRR parameter. In addition, the presented LDO dispose of a Slew-Rate Enhancement function, which can be activated externally. In all cases of this feature activation, the measurement proved its expected and correct function with reducing the settling time value and, depending on the direction of the output current change, also the voltage value for overshoot or undershoot.

This paper presents the design and measurement results of tunable Relaxation Oscillator ($\mathbf{R x O}$) proposed in standard 65 nm CMOS technology. The proposed RxO achieves the wide oscillation frequency range with fine tunability and low power consumption. The achieved results were obtained by measuring the prototype chip and show that the proposed oscillator can be tuned within the range of 72 kHz to 123 MHz, with a tuning step below 0.77 % for digital tuning and$0.53 \% / \text{mV}$for analog tuning with respect to the absolute value of the oscillation frequency. The low power consumption from$1 \text{nW} / \text{kHz}$to$23 \text{nW} / \text{kHz}$was observed. The figure of merit of 64 dB has been found to demonstrate an excellent dynamic range with fine tunability features.

This paper presents tunable voltage reference (TVR) designed in a standard general purpose 65nm CMOS technology. Designed circuit is based on two-transistor (2T) voltage reference (VR) with digitally controlled operational amplifier (OPAMP). Developed TVR provides stable output voltage from 0.38 V to 1.1 V with non-linear tuning step under 0.5% of the output voltage (from 1.9 mV to 2.9 mV). The supply voltage in the range from 0.91 V to 1.5 V is used. The circuit offers parameter PSRR = -53.59 dB (at 1 kHz) and line regulation (LNR) of 0.35% in the worst case. The required area is 0.0185 mm2. The proposed TVR was used to precise frequency tuning of oscillator. Provided results are obtained from both simulations and measurement of the manufactured ASIC prototype.

This paper presents indirect Maximum Power Point Tracking (MPPT) method for solar-powered energy harvester. MPPT is based on Constant Voltage algorithm with enhancement in form of adaptive tuning step. Fully integrated digital control circuit is part of Pulse Frequency Modulation (PFM) control that ensures the maximum energy extraction from the solar cell by adjusting switching frequency of Voltage Converter (VC). Fully on-chip inductor-based step-up converter provides regulated output voltage$\mathrm{V}_{\text{out}}=1.5\mathrm{V}$under different irradiance conditions. The developed system manufactured in a standard 65 nm CMOS technology is self-powered using two solar cells. The energy harvester can be used as a power supply for energy-autonomous electronic devices or low-power applications.

This work presents a dedicated method of analog integrated circuit (IC) autocalibration, which was used to calibrate a voltage reference with the output voltage value of 96 mV . The reference accuracy might be significantly influenced by fluctuations in the manufacturing process. The essence of this technique is to suppress this undesired influence of process variations in terms of the corner conditions of 130 nm CMOS technology. All analog parts of the proposed autocalibration system are presented at the transistor level. The output of the calibration subcircuit is a digital signal controlling the autocalibration.