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Sushma Prasad

dblp:298/8799 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2024
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1 · 1 since 2021Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware accelerators and domain-specific architectures · 73% Processor architecture and microarchitecture · 21% Cloud and datacenter computing · 6%
Artificial intelligence
1 paper
Efficient and distributed learning · 100%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
machine learning accelerator
1.322024
Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs · ICML 2024
Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial Product · ISCA 2021
Machine learning › Efficient and distributed learning
model compression
0.812024
Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs · ICML 2024
Machine learning › Efficient and distributed learning › model compression
quantization
0.812024
Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs · ICML 2024
Hardware accelerators and domain-specific architectures › machine learning accelerator
inference accelerator
0.512021
Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial Product · ISCA 2021
Processor architecture and microarchitecture › instruction-level parallelism
VLIW
0.512021
Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial Product · ISCA 2021

Methods — techniques the papers use, named apart from their topics

student's t-distribution · 1.5pareto analysis · 1.5
YearPublicationVenuePosition
2024 Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs
abstract
The increasing size of large language models (LLMs) traditionally requires low-precision integer formats to meet strict latency and power demands. Yet recently, alternative formats such as Normal Float (NF4) have increased model accuracy at the cost of increased chip area. In this work, we first conduct a large-scale analysis of LLM weights and activations across 30 networks and conclude that most distributions follow a Student’s t-distribution. We then derive a new theoretically optimal format, Student Float (SF4), that improves over NF4 across modern LLMs, for example increasing the average accuracy on LLaMA2-7B by 0.76% across tasks. Using this format as a high-accuracy reference, we then propose augmenting E2M1 with two variants of supernormal support for higher model accuracy. Finally, we explore the quality and efficiency frontier across 11 datatypes by evaluating their model accuracy and hardware complexity. We discover a Pareto curve composed of INT4, E2M1, and E2M1 with supernormal support, which offers a continuous tradeoff between model accuracy and chip area. For example, E2M1 with supernormal support increases the accuracy of Phi-2 by up to 2.19% with 1.22% area overhead, enabling more LLM-based applications to be run at four bits. The supporting code is hosted at https://github.com/cornell-zhang/llm-datatypes.
Jordan Dotzel, Yuzong Chen 0001, Bahaa Kotb, Sushma Prasad, Sheng Li 0007, Mohamed S. Abdelfattah, Zhiru Zhang
ICML4
2021 Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial Product
abstract
Google deployed several TPU generations since 2015, teaching us lessons that changed our views: semi-conductor technology advances unequally; compiler compatibility trumps binary compatibility, especially for VLIW domain-specific architectures (DSA); target total cost of ownership vs initial cost; support multi-tenancy; deep neural networks (DNN) grow 1.5X annually; DNN advances evolve workloads; some inference tasks require floating point; inference DSAs need air-cooling; apps limit latency, not batch size; and backwards ML compatibility helps deploy DNNs quickly. These lessons molded TPUv4i, an inference DSA deployed since 2020.
Norman P. Jouppi, Doe Hyun Yoon, Matthew Ashcraft, Mark Gottscho, Thomas B. Jablin, George Kurian, James Laudon, Sheng Li 0007, Peter C. Ma, Thomas Norrie, Nishant Patil, Sushma Prasad, Cliff Young, Zongwei Zhou, David A. Patterson 0001
ISCA13