Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Andrea Stevanato

dblp:299/0008 · DBLP profile ↗
← Back
5ranked-venue papers
3as first author
5since 2021 · last 2025
0000-0002-6367-3638ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author · 2 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Embedded and real-time systems · 60% GPUs and heterogeneous computing · 21% Performance modeling and evaluation · 18%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
GPUs and heterogeneous computing
deep learning on GPUs
0.912025
Real-Time Multitasking of Deep Neural Networks With Nvidia Tensorrt · RTSS 2025
Embedded and real-time systems
real-time scheduling
0.912025
Real-Time Multitasking of Deep Neural Networks With Nvidia Tensorrt · RTSS 2025
Embedded and real-time systems › real-time scheduling
timing predictability
0.912025
Real-Time Multitasking of Deep Neural Networks With Nvidia Tensorrt · RTSS 2025
Embedded and real-time systems
multicore real-time systems
0.812024
Learning Memory-Contention Timing Models With Automated Platform Profiling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024

Methods — techniques the papers use, named apart from their topics

fixed-priority limited-preemptive scheduling · 0.9design-time optimization · 0.9response time analysis · 0.8microbenchmarking · 0.8machine learning for timing models · 0.8
YearPublicationVenuePosition
2025 Real-Time Multitasking of Deep Neural Networks With Nvidia Tensorrt
abstract
Graphics processing units (GPUs) are often employed to accelerate the inference of deep neural networks (DNNs) in cyber-physical systems to implement advanced perception and control functionalities. Frameworks for GPU-accelerated DNN inference typically aim at maximizing the processing throughput rather than focusing on providing a predictable timing behavior, which is crucial for time-sensitive cyber-physical systems. This work proposes a framework for GPU-accelerated inference of DNNs on GPU-based embedded platforms in multitasking scenarios, which provides enhanced timing predictability using a design-time optimization procedure of the DNN workload and a specialized method to schedule the GPU acceleration requests of the DNNs at runtime based on fixed-priority limitedpreemptive scheduling. Fine-grained control of the inference is achieved by splitting the DNNs into smaller chunks, which are then scheduled using a specialized real-time scheduling mechanism. Experimental results on commercial embedded platforms report significant improvements in terms of schedulability.
Federico Aromolo, Andrea Stevanato, Alessandro Biondi 0001, Giorgio C. Buttazzo
RTSS2
2024 Learning Memory-Contention Timing Models With Automated Platform Profiling
abstract
Commercial off-the-shelf (COTS) multicore platforms are often used to enable the execution of mixed-criticality real-time applications. In these systems, the memory subsystem is one of the most notable sources of interference and unpredictability, with the memory controller (MC) being a key component orchestrating the data flow between processing units and main memory. The worst-case response times of real-time tasks is indeed particularly affected by memory contention and, in turn, by the MC behavior as well. This article presents FrATM2, a Framework to Automatically learn the Timing Models of the Memory subsystem. The framework automatically generates and executes micro-benchmarks on bare-metal hardware to profile the platform behavior in a large number of memory-contention scenarios. After aggregating and filtering the collected measurements, FrATM2 trains MC models to bound memory-related interference. The MC models can be used to enable response-time analysis. The framework was evaluated on an AMD/Xilinx Ultrascale+ SoC, collecting gigabytes of raw experimental data by testing tents of thousands of contention scenarios.
Andrea Stevanato, Matteo Zini, Alessandro Biondi 0001, Bruno Morelli, Alessandro Biasci
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2023 Virtualized DDS Communication for Multi-Domain Systems: Architecture and Performance Evaluation of Design Alternatives
abstract
Modern applications for cyber-physical systems, such as autonomous driving, are more and more often characterized by the interconnection of software components with mixed levels of safety and security deployed on the same hardware platform. Virtualization by means of hypervisor technology is notably the most common approach to allow for the integration of such software components upon the same platform. The Data Distribution Service (DDS) is a publisher/subscriber middleware protocol that is establishing as a reference solution to put in communication distributed software components. Given these developments, the need for efficiently supporting DDS-based communication in virtualized systems is emerging in several industrial fields, especially when DDS communications interest in-platform software components. This paper presents the design of a virtualized DDS communication architecture for multidomain systems based on para-virtualization and hypervisor technology. The design is then specialized and implemented for the popular Xen hypervisor and Linux operating system, under which a set of implementation options are systematically studied and compared with a wide experimental evaluation.
Andrea Stevanato, Alessandro Biondi 0001, Alessandro Biasci, Bruno Morelli
RTAS1
2021 An Evaluation of Adaptive Partitioning of Real-Time Workloads on Linux
abstract
This paper provides an open implementation and an experimental evaluation of an adaptive partitioning approach for scheduling real-time tasks on symmetric multicore systems. The proposed technique is based on combining partitioned EDF scheduling with an adaptive migration policy that moves tasks across processors only when strictly needed to respect their temporal constraints. The implementation of the technique within the Linux kernel, via modifications to the SCHED_DEADLINE code base, is presented. An extensive experimentation-has been conducted by applying the technique on a real multi-core platform with several randomly generated synthetic task sets. The obtained experimental results highlight that the approach exhibits a promising performance to schedule real-time workloads on a real system, with a greatly reduced number of migrations compared to the original global EDF available in SCHED_DEADLINE.
Andrea Stevanato, Tommaso Cucinotta, Luca Abeni, Daniel Bristot de Oliveira
ISORC1
2021 A Multi-Domain Software Architecture for Safe and Secure Autonomous Driving
abstract
This work aims at making Apollo, a popular autonomous driving framework, safer and more secure by designing a multi-domain architecture, where its components are split between a feature-rich domain running Linux and a critical domain running a real-time operating system (RTOS). The two domains are isolated by a hypervisor. We implemented a prototype where the control component has been ported from Linux to the Erika automotive-grade RTOS, and we discuss a number of challenges that have been faced in moving the component to Erika. The proposed solution has been experimentally evaluated by measuring the latencies involving processing paths passing through the control component.
Luca Belluardo, Andrea Stevanato, Daniel Casini, Giorgiomaria Cicero, Alessandro Biondi 0001, Giorgio C. Buttazzo
RTCSA2