EDBT 2026 Demo / reviewers in the wild / expert
Philipp Machauer
dblp:299/3273
· DBLP profile ↗
3ranked-venue papers
0as first author
3since 2021 · last 2024
0009-0001-6017-8789ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Processor architecture and microarchitecture · 45% Reconfigurable computing and FPGAs · 41% Parallel and multicore computing · 14% | |
| Network and information security
1 paper |
Hardware security and side channels · 100% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture
SIMD |
0.5 | 1 | 2021 | Fair Scheduling for AVX2 and AVX-512 Workloads · USENIX ATC 2021 |
Reconfigurable computing and FPGAs
covert channel |
0.2 | 1 | 2024 | Covert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs via Covert Channels · FPGA 2024 |
Reconfigurable computing and FPGAs › FPGA virtualization
multi-tenant FPGA |
0.2 | 1 | 2024 | Covert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs via Covert Channels · FPGA 2024 |
Parallel and multicore computing › parallel scheduling
thread scheduling |
0.1 | 1 | 2021 | Fair Scheduling for AVX2 and AVX-512 Workloads · USENIX ATC 2021 |
Methods — techniques the papers use, named apart from their topics
power hammering · 1.5covert channel · 1.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | Covert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs via Covert ChannelsabstractWith the rise of AI, end of Moore's law, and the digitization of public services, the demand for accelerated computing is growing. To address this demand, major cloud service providers like Amazon Web Services, Microsoft Azure, and Google Cloud Platform have incorporated FPGA instances into their infrastructure with efficient and adaptable resource allocation models. Interest is increasing in multi-tenant FPGAs, which enable multiple users to utilize FPGA resources concurrently, while the FPGA can be split into smaller sections, one per tenant. Nevertheless, it introduces significant security vulnerabilities. For instance, by configuring a malicious circuit in one tenant's section of the FPGA, attacks that cause faults or crash the entire FPGA become feasible, affecting other tenants. By splitting an FPGA into smaller fractions, a single tenant has less potential to cause catastrophic outcomes. However, in this paper, we propose another threat, which is to perform an attack where several malicious tenants coordinate an attack using an unintended covert channel. We practically verify this possibility and introduce such a synchronized and coordinated voltage drop attack from multiple malicious tenants. For synchronization, the malicious tenants use a voltage-based covert channel. Our results show that the communication is robust reaching less than 1% packet error rate and that the attack is successful and avoids state-of-the-art countermeasures. Hassan Nassar, Philipp Machauer, Dennis Gnad, Lars Bauer, Mehdi Baradaran Tahoori, Jörg Henkel |
FPGA | 2 |
| 2024 | DoS-FPGA: Denial of Service on Cloud FPGAs via Coordinated Power HammeringabstractThe adoption of FPGA instances by major cloud service providers (CSPs) reflects the growing demand for accelerated and heterogeneous computing across various applications, e.g., AI. To improve the efficiency, utilization and virtualization, multi-tenant FPGAs allow multiple users to utilize FPGA resources concurrently, with each FPGA partition assigned to a separate tenant. However, this introduces significant security vulnerabilities, such as the potential for attacks by configuring a malicious circuit in one tenant's FPGA partition. One notable vulnerability is disrupting the FPGA's power distribution network, leading to faults or even crashing the entire FPGA, affecting other tenants. Usually, such an attack requires a considerable amount of resources. A naive solution would be splitting an FPGA into smaller fractions to reduce the potential for successful Power-Hammering by individual tenants and enhance the security. However, our paper demonstrates that even with smaller fractions per tenant, attacks can still occur. We propose the threat of coordinated attacks, where malicious tenants use an unintended covert channel between them. We practically validate this threat in a real cloud computing environment by introducing a synchronized and coordinated power-hammering attack from multiple malicious tenants. These tenants synchronize their actions using a voltage-based covert channel. Our results reveal the success of the attack, surpassing state-of-the-art countermeasures and detection mechanisms with a success rate exceeding 90%, compared to 30% for uncoordinated attacks. Hassan Nassar, Philipp Machauer, Lars Bauer, Dennis Gnad, Mehdi Baradaran Tahoori, Jörg Henkel |
ICCAD | 2 |
| 2021 | Fair Scheduling for AVX2 and AVX-512 Workloads
Mathias Gottschlag, Philipp Machauer, Yussuf Khalil, Frank Bellosa |
USENIX ATC | 2 |