Qiaonian Yu

dblp:299/9384 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Emerging computing paradigms · 83% Processor architecture and microarchitecture · 17%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms
quantum computer architecture
0.512021
Exploiting Different Levels of Parallelism in the Quantum Control Microarchitecture for Superconducting Qubits · MICRO 2021
Emerging computing paradigms › quantum control
quantum control microarchitecture
0.512021
Exploiting Different Levels of Parallelism in the Quantum Control Microarchitecture for Superconducting Qubits · MICRO 2021
Emerging computing paradigms › quantum control
superconducting qubit control
0.512021
Exploiting Different Levels of Parallelism in the Quantum Control Microarchitecture for Superconducting Qubits · MICRO 2021
Processor architecture and microarchitecture
instruction-level parallelism
0.112021
Exploiting Different Levels of Parallelism in the Quantum Control Microarchitecture for Superconducting Qubits · MICRO 2021
Processor architecture and microarchitecture
pipelining
0.112021
Exploiting Different Levels of Parallelism in the Quantum Control Microarchitecture for Superconducting Qubits · MICRO 2021

Methods — techniques the papers use, named apart from their topics

timing control · 0.5parallel instruction scheduling · 0.5
YearPublicationVenuePosition
2021 Exploiting Different Levels of Parallelism in the Quantum Control Microarchitecture for Superconducting Qubits
abstract
As current Noisy Intermediate Scale Quantum (NISQ) devices suffer from decoherence errors, any delay in the instruction execution of quantum control microarchitecture can lead to the loss of quantum information and incorrect computation results. Hence, it is crucial for the control microarchitecture to issue quantum operations to the Quantum Processing Unit (QPU) in time. As in classical microarchitecture, parallelism in quantum programs needs to be exploited for speedup. However, three challenges emerge in the quantum scenario: 1) the quantum feedback control can introduce significant pipeline stall latency; 2) timing control is required for all quantum operations; 3) QPU requires a deterministic operation supply to prevent the accumulation of quantum errors.
Qiaonian Yu, Guanglei Xi, Hualiang Zhang, Fuming Liu, Yarui Zheng, Yicong Zheng, Shengyu Zhang 0002
MICRO4