Danilo Manstretta

dblp:30/10283 · DBLP profile ↗
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6ranked-venue papers
0as first author
3since 2021 · last 2026
0000-0001-6085-2668ORCID · verified

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Systems, architecture and hardware · 6 · 3 since 2021
YearPublicationVenuePosition
2026 A 70 GHz Differential Noise Source for Noise Figure Built-In Self-Test in 22nm FDSOI CMOS
Fabio Pedone, Danilo Manstretta
ISCAS2
2021 A 2nd Order Current-Mode Filter with 14dB Variable Gain and 650MHz to 1GHz Tuning-Range in 28nm CMOS
abstract
An open-loop baseband filter with bandwidth of 1GHz suitable for a receiver operated in the 5G high frequency band (above 24GHz) is presented. The filter is based on a gain boosted Common Gate topology that implements a 2ndorder low-pass filter in the current domain. A frequency-dependent active negative capacitance circuit is used to boost the quality factor of the filter. This not only improves in-band flatness but also increases out-of-band selectivity. A test chip has been realized in 28nm CMOS technology. The filter bandwidth can be programmed from 650 MHz to 1 GHz and the current gain changed by 14 dB, with the power dissipation scaling from 11 mW to 5 mW. In-band IIP3 is +2 dBm and the input noise integrated from 10 MHz to 1 GHz is lower than 170 μVrms.
Karan Sohal, Danilo Manstretta, Rinaldo Castello
ISCAS2
2021 A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs Architecture
abstract
A modified noise/nonlinearity cancellation low-noise transconductance amplifier (LNTA) based on an inductively degenerated common-source stage is proposed to improve linearity. The linearity of the proposed LNTA is analyzed using the Volterra series yielding closed-form equations for the third-order input intercept point (IIP3) that shows excellent matching with the simulation results. The derived equations for noise figure (NF) and IIP3 are simple enough to be used for design optimization. Calculations and simulation results show that the proposed LNTA is more linear than a conventional one, while NF approximately remains unchanged. Another feature of the proposed noise-canceling LNTA is that no additional baseband recombination stage is needed, leading to reduced complexity in the receiver baseband stage. The NF and out-of-band (OOB) IIP3 of the receiver is about 3.3 dB and more than 20 dBm, respectively. The receiver consumes 10.5 mA from 1.8-V supply voltage. The current consumption of the LO divider is 6.5 mA from a dedicated 1-V supply voltage.
Mohsen Javadi, Hossein Miar Naimi, Saheed Tijani, Danilo Manstretta, Rinaldo Castello
IEEE Trans. Very Large Scale Integr. Syst.4
2018 A Sub-1V, 220 μW Receiver Frontend for Wearable Wireless Sensor Network Applications
abstract
Minimizing the dissipated power of RF transceivers is the primarily target to meet the requirements of wearable wireless sensor networks (W-WSN). This paper presents an Ultra-Low Power (ULP) receiver with RF performance exceeding the requirements of the intended application. Thanks to the highly efficient current-reuse Low Noise Amplifier (LNA), followed by a passive mixer, the single-ended 2.4 GHz RF input is down-converted to a low-IF. To generate 25% quadrature LO signals, a high-swing complementary current-reuse Class-C VCO, operating at twice the desired frequency, is followed by a frequency divider-by-two. Furthermore, complex channel selection filtering with center frequency and passband of 2 MHz and 1 MHz respectively is performed utilizing the Gm-boosted Common-Gate baseband stage immediately following the mixer. The proposed receiver is designed and simulated in 40 nm CMOS technology. The entire receiver consumes only 220 μW from 0.8 V supply voltage. It shows DSB-NF of 7.5 dB, conversion gain of 50 dB and image rejection of 20 dB. The proposed design represents almost two times better power efficiency with respect to the state-of-the-art with better or equal RF performance.
Ehsan Kargaran, Danilo Manstretta, Rinaldo Castello
ISCAS2
2018 A TVWS receiver with balanced output self-calibrated IIP2 LNTA employing a low-noise current multiplier
Arianna Coccia, Saheed Tijani, Danilo Manstretta, Rinaldo Castello
Integr.3
2017 A 30μW, 3.3dB NF CMOS LNA for wearable WSN applications
abstract
To meet the requirements of wearable wireless sensor networks (W-WSN), the power dissipation of the RF transceiver has to be drastically reduced. This paper presents an ultra-low power LNA with RF performance exceeding the requirement of the intended application. By reusing the current several times and employing passive gm boosting, the LNA input impedance is reduced by a factor of 24 compared to a single transistor using the same current. The resulting power consumption is only 30μW from a 0.8V supply. Simulation results in 40nm TSMC CMOS technology show NF of 3.3dB and gain of 14.2dB at 2.4GHz. Using a widely accepted FOM for LNAs, the proposed circuit is two times better than the best previously published one.
Ehsan Kargaran, Danilo Manstretta, Rinaldo Castello
ISCAS2