Reconstructing topologically consistent facial geometry is crucial for the digital avatar creation pipelines. Existing methods either require tedious manual efforts, lack generalization to in-the-wild data, or are constrained by the limited expressiveness of 3D Morphable Models. To address these limitations, we propose VGGTFace, an automatic approach that innovatively applies the 3D foundation model, i.e. VGGT, for topologically consistent facial geometry reconstruction from in-the-wild multi-view images captured by everyday users. Our key insight is that, by leveraging VGGT, our method naturally inherits strong generalization ability and expressive power from its large-scale training and point map representation. However, it is unclear how to reconstruct a topologically consistent mesh from VGGT, as the topology information is missing in its prediction. To this end, we augment VGGT with Pixel3DMM for injecting topology information via pixel-aligned UV values. In this manner, we convert the pixel-aligned point map of VGGT to a point cloud with topology. Tailored to this point cloud with known topology, we propose a novel Topology-Aware Bundle Adjustment strategy to fuse them, where we construct a Laplacian energy for the Bundle Adjustment objective. Our method achieves high-quality reconstruction in 10 seconds for 16 views on a single NVIDIA RTX 4090. Experiments demonstrate state-of-the-art results on benchmarks and impressive generalization to in-the-wild data.

Level shifter and floating power supply for high-side channel are major challenges in high-voltage high-frequency DC-DC converters. This paper presents an up to 10 MHz GaN driver suitable for high-power-density automotive electronics. An adaptive short-pulse (ASP) high d$V_{\text {sw}}$/d$t$noise immunity level shifter (LS) with efficient analog noise blanker (ANB) is proposed, achieving 6.8 ns minimum on-time at 10 MHz$f_{\text {sw}}$. A dual-MOS-switches bootstrap (DMSB) circuit is proposed to ensure that the bootstrap (BST) rail achieves saturation (>80%) at 10 MHz frequency by sensing$V_{\text {sw}}$and the low-side gate drive signal. To validate this work, a half-bridge GaN driver has been fabricated in a$0.5~\mu $m 80 V HV CMOS process and the active area is$1.44\times 1.42$mm2. The d$V$/d$t$immunity has been verified both in Buck converter and double pulse conditions, which is up to 46 V/ns at 60V Buck converter and 56 V/ns at 48 V double pulse topology. The proposed DMSB technique achieves a peak efficiency of 86.7% at 10 MHz for 12-to-5V conversion, representing a 6.7% improvement over the conventional approach.

High-quality facial appearance capture has traditionally required costly studio recording. Recent works consider an in-the-wild smartphone-based setup; however, their model-based inverse rendering paradigm struggles with the complex disentanglement of reflectance from unknown illumination. To bridge this gap, we propose to shift the paradigm into training a powerful delighting network as a prior to constrain the optimization. We leverage the OLAT dataset and the rendered Light Stage scans for training, and propose Dataset Latent Modulation (DLM) to seamlessly integrate these heterogeneous data sources. Specifically, by conditioning the core network on learnable source-aware tokens, we decouple dataset-specific styles from physical delighting principles, enabling the emergence of a delighting prior that outperforms existing proprietary models. This powerful delighting prior enables a simple and automatic appearance capture pipeline that achieves high-quality reflectance estimation from casual video inputs, outperforming prior arts by a large margin. Furthermore, we leverage our appearance capture method to transform the multi-view NeRSemble dataset into NeRSemble-Scan, a large-scale collection of 4K-resolution relightable scans. By open-sourcing our model and the NeRSemble-Scan dataset, we democratize high-end facial capture and provide a new foundation for the research community to build photorealistic digital humans.

A current-efficient and fast-transient p-type low-dropout regulator (LDO) for high-current load transient in mobile phone applications is presented in this article. A low-power Auxiliary-Path Push-Pull (AP3) buffer is employed to provide both high charging and discharging current for gate-capacitance (CgP) of power MOS, hence the undershoot and overshoot performance are optimized simultaneously; Meanwhile the auxiliary path of the buffer further accelerates the transient response. Moreover, the shaped-hybrid-bias circuit accurately control the upper and lower limits of EA’s bias current, by this, maximum LDO’s bandwidth is well controlled and keeps proper margin to the self-resonant frequency of off-chip capacitor, which guarantees good loop stability over wide load range. This circuit has been implemented in a 0.18-µm standard 5V CMOS process and occupies a silicon area of 400 × 250 µm2, where 5V devices with a 500-nm minimum channel length are used. With a 1-µF output cap and load steps between 0 A and 270 mA, with 300ns edge time, experimental results show that it features 19/14 mV of undershoot/overshoot at load transient

In this paper, a high-noise-immunity capacitive-coupled level shifter with digital noise blanker (DNB) is presented for GaN drivers. During and after$\text{d}V$/dt transitions, the DNB blanks the common mode noise induced by$\text{d}V$/dt and converts the differential mode noise due to mismatch effect to common mode noise. This enables high$\text{d}V$/dt immunity of 200V/ns and high mismatch tolerance not less than 15%. Moreover, a dynamic discharge control (DDC) circuit prevents coupling capacitor from charging the floating power rail within a wide negative$\text{d}V$/dt transition range and achieves fast reset for high frequency operation. High speed, low power consumption and down to −5V negative floating power rail tolerance are also achieved. The proposed level shifter is fabricated in a 0.5-$\mu \text{m}$BCD process and occupies an active chip area of 0.051mm2. Experimental results confirm that the proposed level shifter works at 50V 50MHz, achieving power consumption of 27.3pJ/transition and 1.26ns average delay with a small figure of merit (5.5(pJ$\cdot $ns)/($\mu \text{m}^{3}\cdot \text{V}$)). The effect of the DDC is confirmed within negative$\text{d}V$/dt transition range of −5V/ns$\sim -50\text{V}$/ns.

This paper presents an anti-overcharged high-dV/dt-immunity capacitive level shifter with dynamic discharge control (DDC) for half-bridge GaN driver. The DDC prevents overcharge of the floating power supply capacitor during high negative dV/dt transitions and is suitable for a wide variation range of negative dV/dt transitions of floating power supply. Moreover, a fault-logic blanking block is introduced to guarantee the robust of output logic during ultra-high dV/dt transitions. The proposed Level shifter is fabricated in a 0.18μm BCD process and occupies an active chip area of 0.034mm2. Simulation results demonstrate that the propagation delay is less than 0.8ns at 50V level shifting and keeps almost constant when the floating ground ranges from -3V to 50V. The positive dV/dt immunity is 300V/ns. The negative dV/dt is 170V/ns under the condition that the level shifting capacitor does not discharge to floating power supply.

A fast-transient, current-efficient low-dropout regulator (LDO) with super transconductance cell (STC) is proposed in this paper. By adopting advanced current amplifier (CA) and dynamic biasing (DB) techniques for the error amplifier (EA), the feedback loop bandwidth can be significantly extended without increasing much quiescent power, which reduces output voltage spikes and response time greatly. Moreover, dynamic reference control (DRC) with robust loop stability is embedded in the LDO to adaptively adjust voltage reference during transient so as to further enhance the slew rate of EA, realizing significant enhancement for the transient performances. This circuit has been implemented in a 0.35μm CMOS process and occupies an active chip area of 456×278 μm2. Experimental results show that it is able to provide 100mA load current at 200mV dropout voltage, with current efficiency of 99.88%. The output voltage spike under maximum load current change in 20ns edge time is less than 11.2mV with a 0.054μs response time. The power-supply rejection (PSR) at 100kHz is -75.6dB.

This paper presents a fully-integrated and fast-transient capacitor-less low-dropout regulator (LDO) with high loop gain and bandwidth in full load range for SoC application. It utilizes a combination of a signal- and transient-current boosting (STCB) error amplifier (EA) with transient enhancement circuit (TEC) and a push-pull differentiator to drive gate capacitance of the power transistor. The STCB-based EA with TEC ensures fast response of the regulator and the differentiator is also adopted to enhance the loop stability while improving transient response simultaneously. Moreover, adaptive biasing is implemented in the circuit to compensate decrease of loop gain and bandwidth at heavy load. The proposed LDO is fabricated in a 0.5μm CMOS process and occupies an active chip area of 0.077mm2. Simulation results demonstrate that it can deliver 100mA load current at 100mV dropout voltage. The voltage spike at the output, undergoing a maximum load current change, is controlled below 300mV and good line/load regulation is achieved at the same time.

Variable on Time (VOT) control is proposed in the paper. Compared to conventional constant on time (COT) control, the on time of VOT control is modulated by output of error amplifier, rather than fixed voltage. VOT controlled buck converter shows significant duty cycle extension than COT control, especially for high switching frequency and wide input/output range applications, such as DVS converters. The duty cycle limitation of COT control is then broken through. The small signal model derivation based on Describing Function (DF) is given. A 1MHz 12V-1.2V buck converter with VOT control is designed with 0.35μm BCD process. Simulation results show that the recovery time is 5μs for 4A load step, and the undershoot voltage is decreased from 50mV to 35mV, by using VOT control. The voltage scaling speed is 20μs/V for 47μF output capacitor. The reference up-tracking shows FOM of 0.42s/(F·V), which is much better than previous works.

A current-efficent, fully integrated low-dropout regulator(LDO) with improved load transient responses for system-on-chips(SoC) is presented in this paper. It makes use of high bandwidth common-gate amplifier and slew-rate enhancement circuit(SRE) triggered by voltage spikes to improve output voltage spike and response time of the LDO greatly. The proposed circuit has been implemented in a 0.35μm standard CMOS process and occupies an active chip area of 0.057mm2. Experimental results show that it can deliver 100mA load current at 150mV dropout voltage. It only consumes 8μA quiescent current and is able to recover within 0.2μs even under the maximum load current change. Consequently, a low-power and ultra-fast capacitor-less LDO can be achieved.