Sixth-generation (6G) edge networks must orchestrate heterogeneous services across massive device populations under strict latency, energy, and privacy constraints. Existing reinforcement-learning (RL) approaches for edge orchestration either ignore semantic task content, lack awareness of network topology, or incur prohibitive communication overhead when deployed in federated settings, limiting applicability to latency-critical 6G scenarios. To address these shortcomings, we propose FedSemGNN, a hierarchical federated RL framework that jointly integrates three complementary capabilities: (i) continual semantic task embeddings regularized by elastic weight consolidation for intent-aware service placement, (ii) graph convolutional network-based topology encoding that captures spatial relationships among edge nodes for structurally coherent decisions, and (iii) a two-level proximal policy optimization architecture with priority-aware scheduling and adaptive semantic thresholds tailored to diverse 6G service classes. Comprehensive evaluation on the EdgeSimPy simulator over 1000 orchestration steps against five representative baselines demonstrates that FedSemGNN achieves 39.08 ms orchestration latency ( 3 . 3 × faster than flat federation), near-perfect semantic fidelity, and 21 × lower communication overhead (0.72 MB). Scalability experiments spanning seven network sizes from 6 to 1000 nodes (a 167 × range) confirm that fidelity is preserved and computation time grows near-linearly. These results position FedSemGNN as a control-plane foundation for privacy-preserving, semantic-aware orchestration in large-scale 6G edge deployments.

Fair competition has become a core value in sports However, the foundation of trust in sports is shaking as doping cases increase Doping is the act of athletes using prohibited drugs Among the drugs, it is easy to classify whether or not these drugs are prohibited drugs among the pills, but as the number of drugs increases, there is inevitably a limit to human ability In this study, AI based pill images are analyzed to identify prohibited drugs A model that automatically classifies drugs was produced using oral drug images Using the dataset provided by AI Hub, a model was produced by learning 160 056 images of 500 oral drugs By applying the CNN model and the SIFT algorithm, a model was produced to analyze and classify external characteristics such as size, color, and shape of a drug Finally, this model had a high classification accuracy of 96 5

Deep neural networks for identifying road cracks have emerged as a crucial field of study, marking a significant advancement in infrastructural maintenance. The proposed research presents a novel Neural Architecture Seeks Large Neural Network for detecting road cracks, featuring 27 convolutional layers and ten modules, leveraging Softmax for classification. Initially, the custom developed dataset contained 30,283 images, expanded to 218,073 images using the Augmented Minority Over-Sampling Technique. For better comparison, only 30,350 images are utilized from this expanded data set. Similarly, the Karlsruhe Institute of Technology and Toyota Technological Institute dataset grew from 30,274 to 217,972 images after Augmented Minority Over-Sampling Technique processing. However, 30,274 images from the original dataset and 30,327 images from the Augmented Minority Over-Sampling Technique dataset have been processed. This normalization process aimed to ensure a balanced comparative study between the original and augmented datasets, minimizing differences and enhancing the reliability of results across the datasets. Utilizing a 70/30 train-test split, the network effectively classifies seven types of crack anomalies. The model achieves 83.7% and 89.8% accuracy on the original and augmented Karlsruhe Institute of Technology and Toyota Technological Institute datasets. The custom dataset reaches up to 91.0% accuracy for post-augmentation, while the pre-augmentation accuracy is 90.7%.

To keep a network secure, a user authentication scheme that allows only authenticated users to access network services is required. However, the limited resources of sensor nodes make providing authentication a challenging task. We therefore propose a new method of security for a wireless sensor network (WSN). Our technique, Secure User Biometric Based Authentication Scheme (SUBBASe), is based on the user biometrics for WSNs. It achieves a higher security level as well as improved network performance. This solution consists of easy operations and light computations. Herein, the proposed technique is evaluated and compared with previous existing techniques. This scheme increases the performance of the network by reducing network traffic, defending against DOS attacks, and increasing the battery life of a node. Consequently, the functionality and performance of the entire network is improved.

A lot of previous works on Map-Reduce improved job completion performance through implementing additional instrumentation modules which collects system level information for making scheduling decisions. However the extra instrumentation may not scale well with increasing number of task-trackers. To this end, we design PADS, a lightweight scheduler which uses time prediction to schedule tasks without additional instrumentation modules. Results shows PADS improves performance by 6%, 12%, and 9% as compared to ESAMR, LA, and DDAS respectively.

Even though flash memory Solid State Drives (FSSDs) outperformed traditional Hard Disk Drives (HDDs), they are still failing to reduce performance gap between microprocessors and storage in computer systems regardless of available high bandwidth. To alleviate this, we propose implementing PCM as main memory in SSDs to replace flash memory. In particular, we present a PCM File Translation Layer (PhaseFTL) that can efficiently manage address translations from host file system to PCM while allowing PCM memory blocks to wear down evenly. PhaseFTL hides PCM's constrains and does not suffer from cache miss because it's address translations are directly linked to the entire mapping table stored on fast PCM main memory.

Current triple-level cell (TLC)-based solids-tate drives used in multimedia storage devices support multichannel access to increase capacity and throughput. Unfortunately, current state-of-the-art FTL algorithms must employ selective caching for inquiring about the address mapping information, which causes low space utilization, a large flash memory requirement, and performance degradation. In this article, the Ca che- b ased Flash Translation Layer (Cab-FTL) is proposed for TLC-based multimedia storage devices. Cab-FTL enhances the read and write performances by achieving high space utilization while reducing the size of the mapping tables to 1.68% compared to DFTL. Despite a caching of the mapping tables in DRAM, Cab-FTL achieves a fast system boot using its fast wake-up mechanism.

The use of MLC/TLC (Multiple/Triple Level Cell) flash memory increases bit error rate, and declines its reliability. To remedy this loss, the Redundancy Array of Inexpensive Disk (RAID) have been widely used to enhance the reliability of the Hard Disk Drive (HDD) and the Solid State Drive (SSD). RAID 5 and RAID 6 ensure high reliability among the various RAID techniques. These RAID techniques exploit parity to recover failures, it is updated whenever data renewed. The RAID 5 technique contains separated parity in a page of different stripes. In the RAID 6 technique, however, parity is written to double. So, RAID 6 guarantees more reliability. These RAID techniques enhance reliability, stability and data recovery capability in SSD. In this paper, we propose the dual RAID technique to use both RAID 5 and RAID 6 in a particular way depending on the data reliability. Reliability of data is divided to relatively high and low, these allows to be determined by user. At this time, data which requires high reliability is managed by the RAID 6 technique, and data which requires low reliability is managed by the RAID 5 technique. The purpose of this technique is to improve data recovery capability and I/O performance in SSD. This technique is evaluated by the trace-driven simulator with Financial1, Financial2, Exchange, and MSN traces. We confirm that the dual RAID technique improves I/O performance with ensuring high reliability.

Flash memory offers attractive features, such as non-volatile, shock resistance, fast access and low power consumption for data storage. However, it has one main drawback of requiring an erase before updating the contents. Furthermore, the flash memory can only be erased for a limited number of times. These characteristics are controlled by a software layer called the flash translation layer (FTL). FTL efficiently manages read, write, and erase operations to enhance the overall performance, and considers wear-leveling to prolong the durability of flash memory. In this article, we identify the logical sector numbers corresponding to random data, termed as hot-LSNs, and distribute them to all available blocks without degrading the performance of the flash memory. From our evaluation, we found that the extra erase operations for distributing the hot-LSNs are very low compared to the overall performance. Even though Hot-LSNs Distributing Wear-Leveling Algorithm (Hot-DL) incorporates wear-leveling in the performance enhancing algorithm, Hot-DL only requires approximately 0.015% of extra erase operations compared to previous well-optimized performance enhancing algorithms, shared buffer scheme.

Flash memory is used widely in the data storage market, particularly low-price MultiLevel Cell (MLC) flash memory, which has been adopted by large-scale storage systems despite its low performance. To overcome the poor performance of MLC flash memory, a system architecture has been designed to optimize chip-level parallelism. This design increases the size of the page unit and the block unit, thereby simultaneously executing operations on multiple chips. Unfortunately, its Flash Translation Layer (FTL) generates many unused sectors in each page, which leads to unnecessary write operations. Furthermore, it reuses an earlier log block scheme, although it generates many erase operations because of its low space utilization. To solve these problems, we propose a hybrid associative FTL (Hybrid-FTL) to enhance the performance of the chip-level parallel flash memory system. Hybrid-FTL reduces the number of write operations by utilizing all of the unused sectors. Furthermore, it reduces the overall number of erase operations by classifying data as hot, cold, or fragment data. Hybrid-FTL requires less mapping information in the DRAM and in the flash memory compared with previous FTL algorithms.