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Nikhil Kriplani

dblp:30/10958 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2012
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 91% Parallel and multicore computing · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
circuit simulation
0.112012
Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Electronic design automation › physical design › circuit partitioning
timing-driven partitioning
0.112012
Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Electronic design automation › circuit simulation
transient analysis
0.112012
Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Parallel and multicore computing › parallel programming models
shared-memory parallelization
0.012012
Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012

Methods — techniques the papers use, named apart from their topics

state-variable-based delay element · 0.1iterative interface · 0.1OpenMP · 0.1
YearPublicationVenuePosition
2012 Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning
abstract
A parallel transient simulation technique for multiphysics circuits is presented. The technique develops partitions utilizing the inherent delay present within a circuit and between physical domains. A state-variable-based circuit delay element is presented, which implements the coupling between two spatially or temporally isolated circuit partitions. A parallel delay-based iterative approach for interfacing delay-partitioned subcircuits is applied, which achieves the reasonable accuracy of nonparallel circuit simulation if both incorporate the same interblock delay. The partitioned subcircuits are distributed to different cores of a shared-memory multicore processor and solved in parallel. A multithreaded implementation of the methodology using OpenMP is presented. Examples showing superlinear speedup compared to unpartitioned single-core simulation using the direct method are presented. This paper also discusses the impact of load balancing and absolute delay on simulation speedup.
Shivam Priyadarshi, Christopher S. Saunders, Nikhil Kriplani, Harun Demircioglu, William Rhett Davis, Paul D. Franzon, Michael B. Steer
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3