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EDBT 2026 Demo / reviewers in the wild / expert

Robert W. Rozeboom

dblp:30/10975 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1976
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test		 0.021976
An implementation of computer aided test generation techniques · DAC 1976
Current problems related to LSI functional testing · DAC 1976
Electronic design automation › hardware verification and test
test generation		 0.021976
An implementation of computer aided test generation techniques · DAC 1976
Current problems related to LSI functional testing · DAC 1976
Electronic design automation › hardware verification and test › test generation
functional test generation		 0.011976
An implementation of computer aided test generation techniques · DAC 1976
Electronic design automation › hardware verification and test
functional testing		 0.011976
Current problems related to LSI functional testing · DAC 1976

Methods — techniques the papers use, named apart from their topics

simulation · 0.0LSI testing · 0.0
YearPublicationVenuePosition
1976 Current problems related to LSI functional testing
abstract
Functional testing problems introduced by the advent of LSI device families are discussed. The problems of using current test generation techniques for LSI functional test design are noted and suggestions for future research are made.
Robert W. Rozeboom
 DAC1
1976 An implementation of computer aided test generation techniques
abstract
A computer program which aids the engineer in developing functional test sequences for digital devices is described. A general overview is given along with specific simulation techniques used. The program has several features unique to the implementation of conventional test generation aids.
Robert W. Rozeboom, Jeri Jane Crowley
 DAC1