Demo Data from EDBT 2026 / reviewers in the wild / expert
Daniel Thiele
dblp:30/11158
· DBLP profile ↗
8ranked-venue papers
6as first author
0since 2021 · last 2016
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 8 · 6 first-authorSoftware engineering, systems software and programming languages · 3 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Embedded and real-time systems · 100% | |
| Computer networks
3 papers |
Vehicular, aerial and satellite networks · 67% Internet of things and sensor networks · 18% Internet architecture and protocols · 15% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Vehicular, aerial and satellite networks
vehicular networks |
0.2 | 1 | 2016 | Invited - Towards fail-operational ethernet based in-vehicle networks · DAC 2016 |
Embedded and real-time systems
real-time communication |
0.2 | 1 | 2015 | Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling · DAC 2015 |
Embedded and real-time systems
real-time scheduling |
0.2 | 1 | 2015 | Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling · DAC 2015 |
Embedded and real-time systems › real-time communication
real-time networks |
0.2 | 1 | 2014 | Exploiting Shaper Context to Improve Performance Bounds of Ethernet AVB Networks · DAC 2014 |
Embedded and real-time systems › cyber-physical system platforms
autonomous driving systems |
0.1 | 1 | 2016 | Invited - Towards fail-operational ethernet based in-vehicle networks · DAC 2016 |
Embedded and real-time systems
cyber-physical system platforms |
0.1 | 1 | 2016 | Invited - Towards fail-operational ethernet based in-vehicle networks · DAC 2016 |
Internet architecture and protocols › local area network
ethernet |
0.1 | 1 | 2014 | Exploiting Shaper Context to Improve Performance Bounds of Ethernet AVB Networks · DAC 2014 |
Methods — techniques the papers use, named apart from their topics
network calculus · 0.8software-defined networking · 0.5compositional formal performance analysis · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2016 | Invited - Towards fail-operational ethernet based in-vehicle networksabstractIn the future, vehicles are expected to act more and more autonomously. The transition towards highly automated and autonomous driving will push the safety requirements for in-vehicle networks. Such networks must support isolation between mixed-critical traffic (e.g. critical control and non-critical infotainment) and must be fail-operational. This paper will present new concepts and mechanisms to achieve these goals in Ethernet-based networks. It will cover advanced topics such as software defined networking (SDN) to implement isolation, fault recovery, and controlled degradation, e.g. to maintain (degraded) operation until the driver takes over or to reach a safe stop. Mischa Möstl, Daniel Thiele, Rolf Ernst |
DAC | 2 |
| 2016 | Formal analysis based evaluation of software defined networking for time-sensitive Ethernet
Daniel Thiele, Rolf Ernst |
DATE | 1 |
| 2016 | Formal worst-case timing analysis of Ethernet TSN's burst-limiting shaper
Daniel Thiele, Rolf Ernst |
DATE | 1 |
| 2016 | Formal worst-case performance analysis of time-sensitive Ethernet with frame preemptionabstractOne of the key challenges in future Ethernet-based automotive and industrial networks is the low-latency transport of time-critical data. To date, Ethernet frames are sent non-preemptively. This introduces a major source of delay, as, in the worst-case, a latency-critical frame might be blocked by a frame of lower priority, which started transmission just before the latency-critical frame. The upcoming IEEE 802.3br standard will introduce Ethernet frame preemption to address this problem. While high-priority traffic benefits from preemption, lower-priority (yet still latency-sensitive) traffic experiences a certain overhead, impacting its timing behavior. In this paper, we present a formal timing analysis for Ethernet to derive worst-case latency bounds under preemption. We use a realistic automotive Ethernet setup to analyze the worst-case performance of standard Ethernet and Ethernet TSN under preemption and also compare our results to non-preemptive implementations of these standards. Daniel Thiele, Rolf Ernst |
ETFA | 1 |
| 2016 | Formal timing analysis of CAN-to-Ethernet gateway strategies in automotive networksabstractDue to increased bandwidth and scalability demands, Ethernet technology is finding its way into recent in-vehicle networks. Tomorrow’s heterogeneous networks will feature legacy buses [e.g. controller area network (CAN) or FlexRay] as well as high-speed Ethernet devices, connected by switches and gateways. As Ethernet offers significantly larger frame sizes than CAN, the efficient transmission of CAN data over an Ethernet backbone depends heavily on the way this data is multiplexed into Ethernet frames. This article focuses on the timing impact introduced by various CAN/Ethernet multiplexing strategies at the gateways. We present a formal analysis method to derive upper bounds on end-to-end latencies for complex multiplexing strategies, which is key for the design of safety-critical real-time systems. We capture complex inter-domain signal paths spanning multiple buses, gateways, and switches and show the applicability in a realistic automotive setup. Daniel Thiele, Johannes Schlatow, Philip Axer, Rolf Ernst |
Real Time Syst. | 1 |
| 2015 | Improving formal timing analysis of switched ethernet by exploiting FIFO schedulingabstractEthernet is an emerging technology in the automotive domain and is capable to overcome the bandwidth and scalability limits of traditional buses like CAN or FlexRay. Formal performance analysis methods are required to verify the timing, e.g. by providing upper bounds on end-to-end latencies, in safety-critical real-time systems, such as automotive control and advanced driver assistance systems. In many real-time capable Ethernet implementations such as IEEE 802.1Q or AVB, frames can be prioritized and frames of equal priority are scheduled in FIFO order at the switch ouput ports. In this paper, we show how to exploit Ethernet's FIFO scheduling in a compositional formal performance analysis to derive tighter timing guarantees. In an automotive Ethernet setup, our proposed analysis leads to a significant reduction in end-to-end latency guarantees. Daniel Thiele, Philip Axer, Rolf Ernst |
DAC | 1 |
| 2014 | Exploiting Shaper Context to Improve Performance Bounds of Ethernet AVB NetworksabstractNew hard real-time Advanced Driver Assistance Systems such as the Collision-Avoidance System push the bandwidth requirements of the communication infrastructure to a new level. Controller Area Network (CAN) and FlexRay are reaching their limits. Ethernet-based automotive networks such as Ethernet AVB are capable of addressing these requirements. However, designing predictable Ethernet networks is more complex than the design of a traditional CAN bus. Formal real-time performance characteristics are key to a successful Ethernet integration. In this paper we present an improved Ethernet AVB performance analysis which exploits traffic-stream correlations. The results are significantly tighter compared to related work. Philip Axer, Daniel Thiele, Rolf Ernst, Jonas Diemer |
DAC | 2 |
| 2012 | Optimizing performance analysis for synchronous dataflow graphs with shared resourcesabstractContemporary embedded systems, which process streaming data such as signal, audio, or video data, are an increasingly important part of our lives. Shared resources (e.g. memories) help to reduce the chip area and power consumption of these systems, saving costs in high volume consumer products. Resource sharing, however, introduces new timing interdependencies between system components, which must be analyzed to verify that the initial timing requirements of the application domain are still met. Graphs with synchronous dataflow (SDF) semantics are frequently used to model these systems. In this paper, we present a method to integrate resource sharing into SDF graphs. Using these graphs and a throughput constraint, we will derive deadlines for resource accesses and the amount of memory required for an implementation. Then we derive the resource load directly from the SDF description, and perform a formal schedulability analysis to check if the original timing constraints are still met. Finally, we perform an evaluation of our approach using an image processing application and present our results. Daniel Thiele, Rolf Ernst |
DATE | 1 |