Stochastic computing (SC) is an approximate computing that represents numerical values based on the probability of ones in bitstreams and performs operations probabilistically. Arithmetic circuits for SC (SC circuits) have attracted attention for applications such as machine learning and image processing due to advantages like not only low area and power consumption but also high fault tolerance. To accelerate stochastic computing based on linear finite state machines (FSMs), parallel implementation of linear FSMs has been proposed. The first objective of this paper is to analyze this parallel implementation method and to clarify the details of the design and the cost-effectiveness of the parallel implementation. Through this analysis, it is shown that hardware cost can be significantly reduced while maintaining high accuracy. As the second objective, this paper proposes a new method of parallel implementation using multi-input linear FSMs in order to further improve the accuracy. Experimental results show these proposed designs can achieve high accuracy while keeping the area and delay low.

Video data is essential for performing computer vision applications. However, errors due to noise or soft errors can be significant, potentially rendering the system invalid. Therefore, detecting such errors is important for these applications. In a real-time video stream, there is no golden reference video data to examine video quality during the functional operation of video processing. To address this issue, the no-reference testing method provides a highly attractive solution. In this work, we propose a no-reference test method that extracts error information from the RGB channels in video data. The proposed method improves test accuracy and precision compared to the previous method designed for human vision when applied to object detection. Experimental results show that more than 90% test accuracy and precision can be achieved. The costs incurred by the proposed method are also discussed. Additionally, based on the results, we further discuss setting different criteria for dynamic and static backgrounds of the target video.

Error tolerant applications such as video processing and machine learning can tolerate some kinds of errors in computation. For error tolerant applications, approximate computing, which aims to reduce computational cost and power consumption by omitting a part of computation within the error tolerance, has been attracting attention in recent years. As a kind of approximate computing with logic circuits for error tolerant applications, various approximate multipliers, which can produce approximate products with small hardware cost, have been proposed. Because such approximate multipliers are employed for error tolerant application requiring high reliability, e.g., autonomous systems, the reliability of the multipliers is one of important issues. In this paper, we focus on three types of approximate multipliers with recovery schemes and discuss the reliability of the approximate multipliers. According to fault acceptability, first, we propose a reliability model of approximate multipliers used for error tolerant applications. With this model, we analyze the relationship between the error recovery ability of the approximate multipliers and their reliability, and then discuss the design of approximate multipliers that can maximize their reliability. Experimental results clarify the optimal designs in terms of the reliability under several situations with different fault occurrence probabilities and error tolerance levels.

As one of test methodologies for image processing circuits, a no-reference test scheme based on false-edge detection has been proposed. Because this scheme does not require any reference circuit or reference data to detect faults, it can reduce test cost. In this paper, we discuss an improvement of the false-edge detection for no-reference test scheme. We analyze the misjudged cases by the previous scheme and clarify that the block-based image processing, which is a general way to process images, is one of the reasons of the misjudgment. Based on this analysis, we improve the false-edge detection by extending the definition of the false-edge. Experimental results show that this improvement can enhance the ability of the false-edge detection, so that it can achieve high test accuracy without large computational overhead.

In safety critical systems, e.g., automotive systems, the concept of fail-operational is very important. In this paper we focus on an approximate voting scheme called IDMR (Inexact Double Modular Redundancy), which can detect an error of the output of the duplicated system and correct the error approximately if the significance of the error is within a certain limit; The systems with IDMR can operate continuously even if a fault occurs in the system, i.e., the systems are fail-operational. To enhance the ability of IDMR scheme, we propose an extended architecture for IDMR scheme, which is called E-IDMR (Extended IDMR). The proposed E-IDMR can correct large errors that cannot be corrected by IDMR, so that the systems with E-IDMR achieve higher fail-operational ability than those with IDMR. Application to automotive ABS and LKAS shows that the proposed E-IDMR is more effective for implementation of these fail-operational systems.

Register-transfer level (RTL) scan design aims at optimizing the scan logic as well as the original logic during logic synthesis by modifying a given RTL description to make every register scannable. The modified RTL description, however, is not uniquely determined for realizing the scan functionality, and therefore, one should carefully modify the description because different descriptions with the same functionality can yield different gate level (GL) circuits in terms of area/delay in practice. In this paper, RTL descriptions are presented for constructing intended scan paths that make use of existing RTL modules such as multiplexers (MUXs) and operational units to reduce the area overhead incurred by scan insertion. Such descriptions have been derived from preliminary experiments that extensively analyze the correspondence between a scan description, its structural interpretation in logic synthesis and the synthesized GL circuit. This paper also presents an algorithm for determining scan paths that maximally exploit effective RTL structures where existing MUXs can be utilized for scan path construction with low area overhead. Experimental results show that the proposed algorithm together with structure-aware scan descriptions is effective in reducing area overhead.

Stochastic computing (SC), which is an approximate computation with probabilities, has attracted attention owing to its small area, small power consumption and high fault tolerance. In this paper, we focus on the fault tolerance of SC with linear finite state machines (linear FSMs). We show that state assignment of FSMs considerably affects the fault tolerance of FSM-based SC circuits, and present a Markov model representing the impact of the state assignment on the behavior of faulty FSMs. Furthermore, we propose a heuristic algorithm for appropriate state assignment that can mitigate the influence of the transient faults. Experimental results show that the proposed state assignment can significantly reduce the influence of the faults.

Reliable built-in self-test (Reliable BIST) scheme equips to be tolerant of faults, which occur in embedded BIST circuits. To realize reliable BIST, it is required to recover itself from transient errors of its embedded BIST circuits. In this paper, we propose a self-error-correctable response analyzer (RA) for a reliable BIST scheme. Experimental results show that test-reliability of SECRA is superior to TMR MISRs on the assumption that transient faults occur in RA during testing CUTs.

In this paper, we focus on fault-acceptability-based logic simplification for error tolerant application. We propose a practical (or cost-effective) logic simplification algorithm. The proposed algorithm (1) avoids acceptability identification for faults that are potentially unacceptable and (2) isolates redundancy identification procedure from acceptability identification. Experimental results show that, compared with a previous algorithm, the proposed algorithm can reduce the computational effort without losing the ability of logic simplification.

This paper discusses a controller design in high-level synthesis to tolerate multi-cycle transient faults under the situation where its datapath has the ability of tolerating such faults. It focuses especially on the control signal generator (or output logic) that is a component of the controller feeding control signals to the datapath in a controller-datapath system, and presents a method of controller synthesis that leverages the error correction/detection ability of the datapath. Experimental results show that the proposed method can synthesize fault tolerant controllers with small area overhead compared with the conventional method based on triple modular redundancy (TMR).

Error tolerant applications can tolerate specific errors, whose frequency and/or severity are within certain limits. This error tolerability is greatly instrumental in simplifying logic circuits for such applications. In this paper, we propose a logic simplification method for error tolerant application. Owing to error tolerance, we have an opportunity to complement several minterms of a given logic function within a threshold; if appropriate minterms are selected to be complemented, the given function can be greatly simplified. To select such minterms, we focus on two transformations, expansion and reduction, of prime implicants of the given logic function, and discuss the effect of the transformations on logic simplification. The proposed algorithm utilizing such transformations can efficiently find effective minterm complement. Experimental results show that, compared with a previous method, which employs only expansion of prime implications, the proposed algorithm can produce smaller logic circuits with reasonable computational effort.

Stochastic computing, which is an approximate computation with probabilities (called stochastic numbers), draws attention as an alternative method of deterministic computing. In this paper, we discuss a design of compact and accurate stochastic circuits. Stochastic circuits are known as a way to stochastically compute complex calculation at low hardware cost, while stochastic number generators (SNGs), which are used for converting deterministic numbers into stochastic numbers, account for a large fraction of the circuits. To reduce such SNGs in stochastic circuits, we propose a technique to share random number generators with several SNGs. This sharing method employs circular shift of the output of LFSRs to reduce the correlation between stochastic numbers. We also discuss the influence of input correlation around a multiplexer, which is a scaled adder for stochastic computing, so as to avoid over reducing the input correlation. Application of the proposed techniques to two stochastic image processing shows the reduction in the size of SNGs without greatly sacrificing accuracy.

Reliable built-in self-test (Reliable BIST) is a scheme in which embedded circuits used for self-testing circuits-under-test (CUTs) are designed to be tolerant of their faults. Reliable BIST is especially important for highly reliable on-line testing for real-time system, reliable BIST is required to recover itself from transient errors of its embedded BIST circuits. In this paper, we propose a transient fault tolerant test pattern generator (TPG) for a reliable BIST scheme. The proposed TPG, called EC-TPG, can correct (or mask) errors that occur on itself during testing CUTs, so that it can enhance its test-reliability, which is the probability that the TPG can generate correct (expected) test patterns. We analyze the test-reliability of EC-TPG in order to show that EC-TPG has high test-reliability. Furthermore we demonstrate that, in on-line BIST for real-time systems, EC-TPG can achieve higher test-reliability compared with a test re-execution scheme with error detection through some case studies.

Many test designs (or DFTs: designs-for-testability) have been proposed to overcome various issues around LSI testing. In this paper, we propose a cost and benefit model for comparing several test designs in terms of the final profit of logic LSI design and manufacturing. Test designs can affect chip area, testing time, test generation time and fault coverage; in the proposed model, we clarify the relationship among these factors for major three test designs: scan design, built-in self-test (BIST) design and test compression design. The proposed model reveals the final profit for each test design in a given LSI design and manufacturing environment, so that it can designate a suitable test design in the early stage of LSI design flow. We show an example of application of the proposed model for test design selection in a given environment.

Test compression / decompression is one of effective methods for testing today's VLSI. In this paper, we discuss test compression with image compression algorithms, e.g., JPEG algorithm. Image compression algorithms can not only achieve considerably high compression but also require no additional decompression circuity on a chip under test if the chip includes image decoders. Moreover, we propose a method for generating seeds (or compressed test data) in the case where a JPEG decoder is utilized as a test decompressor. Although JPEG algorithm carries out lossy compression, given a test data, the proposed algorithm can search seeds that can be decompressed to another test data preserving the test quality of the given test data, and produce a small set of seeds with high fault coverage. Experimental results show the proposed method can achieve compression ratio comparable with several previous test compression methods without larger hardware overhead.

As the advance in semiconductor technology, the tolerance for transient faults caused by particle strike, called SET (single event transient), becomes an important issue, and moreover future technologies bring the possibility of occurrence of long duration errors spanning across multiple cycles of the circuits due to particle strike. In this paper we discuss high-level synthesis for multi-cycle transient fault tolerant datapaths. Clarifying the conditions for multi-cycle error correctability and detectability of multi-cycle transient fault tolerant datapaths, we propose a heuristic algorithm for finding optimal operator binding of kc-cycle error correctable / kd-cycle error detectable datapaths with minimum operators. The method focuses on only transient faults (not permanent ones), and therefore it can derive appropriate designs necessary and sufficient for tolerance of SET avoiding use of excessive hardware resources.

The hybrid delay scan design in which some flip flops (FFs) are controlled as skewed-load FFs and the others are controlled as broad-side FFs was proposed. Noticing that the hybrid delay scan design potentially has a capability of two test application modes: one is the broad-side test mode, and the other is the hybrid test mode, we present a hybrid test application of the two test modes in the hybrid delay scan design. In addition, we also address a way of skewed-load FF selection based on propagation dominance of FFs in order to take advantage of the hybrid test application. Experimental results for ITC'99 benchmark circuits show that the proposed hybrid scan design with the hybrid test application can achieve higher fault coverage than the previous hybrid scan design.

Fail-soft systems with reconfigurable devices, which recover themselves by repeating isolation of faulty portions with graceful degradation, have been proposed. In this paper, we proposed a fail-soft system on an FPGA and discuss the performance and availability of the system. The proposed system can infer the type of faults from obtained errors, and then adaptively reconfigure itself autonomously, so that it can achieve high availability while keeping high performance. Case studies show that the proposed system can achieve high availability with high performance by avoiding excessive recovery.

Threshold testing, which is an LSI testing method based on the acceptability of faults, is effective in yield enhancement of LSIs and selective hardening for LSI systems. In this paper, we propose test generation models for threshold test generation. Using the proposed models, we can efficiently identify acceptable faults and generate test patterns for unacceptable faults with a general test generation algorithm, i.e., without a test generation algorithm specialized for threshold testing. Experimental results show that our approach is practically effective.

Test data compression /decompression schemes for testing SoCs can reduce test application cost. A drawback of the previous schemes, however, is that a decompressor must be embedded in an SoC under test. In this paper, we target the testing of SoCs with multimedia cores and introduce a scheme of test compression / decompression with the decoding function in the multimedia cores. This scheme can utilize the decoder and encoder in a multimedia core for compressing and decompressing test data, and consequently it requires slight hardware overhead. As an example of the proposed scheme, we focus on a lossless variable-length coding (VLC) in the JPEG algorithm, and propose a test compression / decompression method using the VLC decoder. We also propose a test generation method for this scheme. Experimental results show that the test compression with the VLC can achieve high compression ratio and the proposed test generation method can increase the compression ratio.

This paper proposes a self-test method of dynamically reconfigurable processors (DRPs) without area overhead. This method constructs a test frame of processor elements (PEs) such that it consists of test pattern generators, response analyzers and PEs under test, and switches several test frames dynamically so as to test all the PEs. Since the number of contexts and test application time are subject to the structure of test frames, we design several test frames with different structures and discuss the relationship of the structures to the number of contexts and test application time. Based on this discussion, we can construct the best test frame according to a given test environment.

We present a graph model and an ILP model for optimal TAM design for transparency-based SoC testing. The proposed method is an extension of (Chakrabarty, 2003) so that not only the system-level cost but also the core-level cost can be simultaneously taken into consideration during the optimization process. We also relax the constraints by considering test dataflows and extend it to be able to handle the case where cores cannot be made transparent due to IP protection. The proposed ILP model can represent various problems including the same problem as (Chakrabarty, 2003) and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to (Chakrabarty, 2003).

Test compression / decompression method using variable length coding is an efficient method for reducing the test application cost, i.e., test application time and the size of the storage of an LSI tester. However, some coding imposes slow test application, and consequently it requires large test application time in spite of its high compression. In this paper, we clarify the fact that test application time depends on the compression ratio and the length of codewords, and then propose a new Huffman-based coding method for achieving small test application time in a given test environment. The proposed coding method adjusts both of the compression ratio and the length of the cord words to the test environment. Experimental results show that the proposed method can archieve small test application time while keeping high compression ratio.

Hierarchical test generation is an efficient method of test generation for VLSI circuits. In this paper, we study a test plan generation algorithm for hierarchical test based on strong testability. We propose a heuristic algorithm for finding a control forest requiring a small number of hold functions by improving an existing test plan generation algorithm based on strong testability. Experimental results show that the proposed algorithm is effective in reducing additional hold functions, i.e., reducing hardware overhead and delay penalty of datapaths.

Test compression/decompression scheme using variable-length coding, e.g., Huffman coding, is efficient in reducing the test application time and the size of the storage on an LSI tester. In this paper, we propose a model of a decompressor with a buffer for variable-length coding and discuss its property. The embedded buffer allows the decompressor to operate at any input and output speed without a synchronizing feedback mechanism between an ATE and the decompressor. Moreover, we propose a method for reducing the size of the buffer embedded in the decompressor. Since the buffer size depends on the input order of test vectors, test vector reordering can reduce the buffer size. The proposed algorithm is based on fluctuations in buffered data for each test vector. Experimental results show a case where the ordering algorithm can reduce the size of the buffer by 97%.

Test compression/decompression is an efficient method for reducing the test application cost. In this paper, we propose a response compression method based on Huffman coding. The proposed method guarantees zero-aliasing because faulty responses are mapped into code words, not just fault-free ones. Moreover, the method is independent of the fault model and the structure of a circuit-under-test, and uses only the knowledge of the fault-free responses corresponding to a given test input set. Experimental results of the compression ratio and the size of the encoder for the proposed method are presented.

Test compression/decompression is an efficient method for reducing the test application cost. In this paper we propose a test generation method for obtaining test-patterns suitable to test compression by statistical coding. In general, an ATPG generates a test-pattern that includes don't-care values. In our method, such don't-care values are specified based on an estimation of the final probability of 0/1 occurrence in the resultant test set. Experimental results show that our method can generate test patterns that are able to be highly compressed by statistical coding, in small computational time.

In IDDQ testing, it is important to reduce the number of time-consuming IDDQ measurements. Therefore, it is necessary to select a small number of IDDQ measurement vectors in a test sequence for a sequential circuit while fault coverage is nearly maximum. In this paper, we address the selection problem of measurement vectors by introducing a cost function which is defined by the number of measurement vectors and fault coverage. The proposed method for selecting measurement vectors optimizes the cost function so that high fault coverage is obtained by a small number of measurement vectors.

This paper considers a new test generation scheme in which a limitation of the number of tests exists. Since, in this scheme, correct fault coverage cannot be calculated by the representative faults, we present a method for calculating the correct fault coverage by using the weighted fault list. And then we propose a selection-based test generation method which derives a limited number of tests with higher fault coverage. The experimental results for IDDQ testing shows that our test generation method can generate tests with fault coverage close to the maximum fault coverage.

The procedure used in static learning extracts implication relations of the logic circuit. The number of extracted implication relations depends on the order of signal lines processed. In this paper we propose an efficient method to extract implication relations by considering the order of signal lines to be processed. Experimental results show that the proposed order finds more implication relations than others and is effective for redundancy identification.

In logic synthesis the multi-level logic optimization methods using implication analysis has high performance but it needs a lot of computational time because of using test pattern generation to identify redundant faults. In this paper we proposed a fast redundancy identification method using implication relation instead of test pattern generation. Experimental results for benchmark circuits clearly show that the proposed method can accelerate the speed to identify redundancies without declining of the ability of the optimization.