In this paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, hierarchical approaches from UniPhier Soc level, UniPhier processor level, IPP (instruction parallel processor) level, and circuit level are adopted. As SoC level, 1) well functionally isolated 5 major units of UniPhier SoC architecture, 2) dedicated stream DMA controller which can minimize CPU load and memory access. As UniPhier processor level, 1) UniPhier processor consists of IPP with dedicated low power hardware engine, 2) VMP (virtual multi-processor) mechanism with micro sleep which can reduce average power consumption in case of multiple tasks concurrent operation, 3) intermittent operation with the combination of micro-sleep and clock/power down scheme in case of very light load operation. As IPP level, 1) sophisticated instruction fetch buffer mechanism which can reduce more than 50% memory access for instruction fetch. 2) Hierarchical and selective clock gating scheme by detailed clock power analysis and clock activity rate analysis on real application.) Optimized physical implementation with low-power library and selective use of custom macros. As circuit level, mixed body bias technique with fixed Id and fixed Vt control which can realize 85 % delay variation suppressed and 25% ED product improvement compared with the no body bias.

multiple instructions per clock cycle, there are at least four This paper describes a VLSI superscalar processor architecture which can sustain very high performance in numericai applications. The architecture performs instructionlevel scheduling statically by the compiler, and performs outof-order issuing and executing of instructions to decrease the stall on the pipelines that dynamically occurs in execution. In this architecture, a pair of instructions are fetched in every clock cycle, decoded simultaneously, and issued to corresponding execution pipelines independently. For ease of instruction-level scheduling by the compiler, the architecture provider: -i) rimultaneoun execution df almost all pairs of instructions including Store-Stare pair and Load-Store pair, ii) simple, low-latency, and easily-paired execution pipeline structure, and iii) high-capacity muiti-ported floating point registers and integer registers. Enhanced performance by the dynamic decrease of the pipeline hazards is achieved by i) efficient data dependency resolution with novel Directly Tag Compare (DTC) method, ii) non-penalty branch mechanism and simple control dependency resolution, and iii) large data transfer ability by the pipelined data cache and 128 bit wide bus bandwidth. An efficient data dependency resolutioi mechanism, which is realized by using the novel DTC method, synchronized pipeiine operation, and data bypassing network, permits out-of-order instruction issuing and execution. The idea of DTC method is similar to that of dynamic data-flaw architecture with tagged token. The non-penalty branches are realized by three techniques, delayed branch, LOOP instruction that executer counter decrement, compare, and branch in one clock cycle, and non-penalty conditional branch with predicted condition codes. These 'techniques contribute to the decrease of the pipeline stalls occurring at run time. The architecture can achieve 80MFLOPS/80MIPS peak performance at 4OMHz clock and sustain 1.4 to 3.6 times higher performance of simple Multiple Function Unit (MFU) type RISC processors by taking advantage of these techniques.