One of the most important factors in training object recognition networks using convolutional neural networks (CNN) is the provision of annotated data accompanying human judgment. Particularly, in object detection or semantic segmentation, the annotation process requires considerable human effort. In this paper, we propose a semi-supervised learning (SSL)-based training methodology for object detection, which makes use of automatic labeling of un-annotated data by applying a network previously trained from an annotated dataset. Because an inferred label by the trained network is dependent on the learned parameters, it is often meaningless for re-training the network. To transfer a valuable inferred label to the unlabeled data, we propose a re-alignment method based on co-occurrence matrix analysis that takes into account one-hot-vector encoding of the estimated label and the correlation between the objects in the image. We used an MS-COCO detection dataset to verify the performance of the proposed SSL method and deformable neural networks (D-ConvNets) [1] as an object detector for basic training. The performance of the existing state-of-the-art detectors (D-ConvNets, YOLO v2 [2], and single shot multi-box detector (SSD) [3]) can be improved by the proposed SSL method without using the additional model parameter or modifying the network architecture.

The reconfigurable scan network standardized by IEEE std. 1687 offers flexibility in accessing the on-chip instruments, which significantly improves the test cost. In this paper, we present a novel time-multiplexed 1687-network architecture that significantly improves the absolute test application time of systems-on-chip at wafer-level as well as package-levels tests. This architecture leverages: 1) the ever increasing tester channel frequency; 2) the allowed test frequencies at the two test levels; and 3) the flexibility offered by the 1687-network. We also present a test-time calculation method for the proposed network architecture and use it in our experiments. Furthermore, we study the effects of the number of time slots on different parameters.

In[1], the corresponding author was incorrect. The correct corresponding author is Sungju Park.

The scan PUF, which is based-on the power-up states of scan flip-flops, had been proposed to overcome security issues of semiconductor ICs. IC identification, one of those security issues, requires decent uniqueness along with reliability and randomness. This paper presents two efficient PUF elements' selection methods for scan PUF: uniqueunanimous selection method and unique-majority selection method. These methods classify the scan cells according to their trend of power-up states and prioritize them to extract PUF elements. For experiments, enrollment and validation is performed on 15 chips, which are fabricated with 65nm CMOS process. A statistical analysis on experiments verifies the performance of proposed selection methods.

The semiconductor aging is one of the serious threats for the reliability of the system. This paper presents an efficient mechanism for predicting the aging effect. The captured data will be unloaded by shift operation, then verified through the aging monitoring operation. Especially the aging level of automotive semiconductor devices can be estimated by controlling the capture timing. Since the aging monitoring function is efficiently on and off during normal operation, power consumption can be reduced significantly compared with other approaches.

In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories to repair defective cells or bit lines during production test. In many cases, the repair process will not use all spare columns. Schemes have been proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in single error correction - double error detection (SEC-DED). These additional check bits increase the dimensions of the parity check matrix (H-matrix) requiring extra area and delay overhead. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity of logic between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in the reduced area and delay overhead.

Future mobile networks providing multitude of services with large range of QoS requirements has made the importance of Radio Resource Management (RRM) ever more significant. Traditional scheduling schemes have approached resource allocation mainly from a cell point of view to large extent ignoring effects of multi-cell architecture. Recently, Load Matrix (LM) concept has been proposed which facilitates joint management of interference within and between cells for allocation of radio resources. In this paper, we assess the Load Matrix scheduling performance when combined with traditional schedulers. In addition, a new LM algorithm for efficient RRM, called Global Proportional Fair (GPF) is proposed. The results show that GPF algorithm with an appropriate window size outperforms traditional scheduling schemes in terms of both throughput and fairness. It combines the throughput advantage of Max C/I and the fairness advantage of Proportional Fair scheduler.