With the growing demand for satellite network technology in military and commercial applications, a large number of LEO(Low Earth Orbit) satellites have been launched in various countries around the world. One of the most important tasks is to download the data collected by these satellites to the Earth Stations(ESs) for processing. Previous research efforts have focused on how to download satellite-collected data to ESs. They didn't consider the situation that the satellites continuously collect data when downloading data. In this paper, our goal is to optimize the data download from the satellites to the ES in the case of dynamic collection of satellite data. We use inter-satellite links (ISLs) to offload data from heavily loaded satellites to the light ones. We build a topology map based on the interaction time between satellites and the interaction time between the satellite and the ES, and allocate the download time to the satellite carrying the largest amount of data. Then, the time slice is dynamically divided and the inter-satellite scheduling is determined by a way of classifying the idle satellites. Finally, the maximum flow algorithm is applied to determine the specific inter-satellite transmission scheme. In this way, the ES idle time is minimized. Simulations results show that our solution can greatly improve the data download efficiency from the satellites to the ES.

Recent works show bias temperature instability (BTI) is a detrimental hard-aging mechanism in CMOS circuit design. Negative BTI (NBTI) alone degrades circuit speed upwards of 20% over a 10 year life-span. Having the ability to track the actual aging process provides one method to reduce large design margins that are otherwise required to offset circuit aging. This work extends previous research by contributing a sensing scheme that employs on-chip sensors capable of accurately tracking NBTI pMOS current degradations across process, temperature, and varying activity factors. Results show that a 7600$\mu{\hbox {m}}^{2}$sensing area achieves an overall system accuracy of 90% at a voltage threshold precision of 2 mV. We thoroughly describe the sensor design and the underlying statistics used to determine overall accuracy and precision. Furthermore, a novel sensor distribution method is presented that uses an existing scan-chain methodology to mask the overhead of adding the on-chip sensors.

SRAM cell minimum operation voltage (Vmin) exhibits a skewed distribution in the presence of random parametric variations. Standard Monte Carlo (MC) simulation is prohibitively expensive to estimate the tail of the Vmin distribution for large SRAMs. We propose a fast and accurate method to estimate Vmin based on the statistical trend of static noise margin withVDDscaling. Our preliminary work has shown its efficiency for standby Vmin estimation. In this work, we extend the method to estimate read and write Vmin and yield. We also generalize it for both symmetric and asymmetric types of cells. With comparable accuracy, the proposed model offers a huge speedup over standard MC. Compared with an alternative fast MC method, importance sampling, it shows a good agreement with less complexity.

To achieve aggressive standby power reduction for static random access memory (SRAM), we have previously proposed a closed-loop VDDscaling system with canary replicas that can track global variations. In this paper, we propose several techniques to enhance the efficiency of this system for more advanced technologies. Adding dummy cells around the canary cell improves the tracking of systematic variations. A new canary circuit avoids the possibility that a canary cell may never fail because it resets into its more stable data pattern. A built-in self-test (BIST) block incorporates self-calibration of SRAM minimum standbyVDDand the initial failure threshold due to intrinsic mismatch. Measurements from a new 45 nm test chip further demonstrate the function of the canary cells in smaller technology and show that adding dummy cells reduces the variation of the canary cell.

NBTI has been a major aging mechanism for advanced CMOS technology and PBTI is also looming as a big concern. This work first proposes a compact on-chip sensor design that tracks both NBTI and PBTI for both logic and SRAM circuits. Embedded in an SRAM array the sensor takes the form of a 6T SRAM cell and is at least 30x smaller than previous designs. Extensively reusing the SRAM peripheral circuitry minimizes control logic overhead. Sensing overhead is further amortized as the sensors can be both reconfigured and recycled as functional SRAM cells, potentially increasing SRAM yield when other bit cells fail due to initial process variation or long time aging effects. The paper also proposes a variation-aware sensor system design methodology by quantifying and leveraging the tradeoff between the size and number of sensors and the system sensing precision. Design examples show that a system of 500 sensors can achieve 4mV precision with 98.8% confidence, and a system of 1K sensors designed for 1M SRAM bit cells achieves 2000x area overhead reduction compared to a worst-case based approach.

The data retention voltage (DRV) defines the minimum supply voltage for an SRAM cell to hold its state. Intra-die variation causes a statistical distribution of DRV for individual cells in a memory array. We present two fast and accurate methods to estimate the tail of the DRV distribution. The first method uses a new analytical model based on the relationship between DRV and static noise margin. The second method extends the statistical blockade technique to a recursive formulation. It uses conditional sampling for rapid statistical simulation and fits the results to a generalized Pareto distribution (GPD) model. Both the analytical DRV model and the generic GPD model show a good match with Monte Carlo simulation results and offer speedups of up to four or five orders of magnitude over Monte Carlo at the 6σ point. In addition, the two models show a very close agreement with each other at the tail up to 8σ. For error within 5% with a confidence of 95%, the analytical DRV model and the GPD model can predict DRV quantiles out to 8σ and 6.6σ respectively; and for the mean of the estimate, both models offer within 1% error relative to Monte Carlo at the 4σ point.

This paper examines the impact of technology scaling to 22 nm on sub-threshold circuit design and proposes several solutions for sub-threshold circuits in new processes. To maintain energy-efficient sub-threshold operation, we must reduce variation and suppress leakage current. To combat random variation and minimize energy for nodes below 45 nm, we show that special strategies are needed for different categories of sub-threshold circuits.

This paper analyzes write ability for SRAM cells in deeply scaled technologies, focusing on the relationship between static and dynamic write margin metrics. Reliability has become a major concern for SRAM designs in modern technologies. Both local mismatch and scaled VDD degrade read stability and write ability. Several static approaches, including traditional SNM, BL margin, and the N-curve method, can be used to measure static write margin. However, static approaches cannot indicate the impact of dynamic dependencies on cell stability. We propose to analyze dynamic write ability by considering the write operation as a noise event that we analyze using dynamic stability criteria. We also define dynamic write ability as the critical pulse width for a write. By using this dynamic criterion, we evaluate the existing static write margin metrics at normal and scaled supply voltages and assess their limitations. The dynamic write time metric can also be used to improve the accuracy of VCCmin estimation for active VDD scaling designs.

This paper describes the strong effects on sub-threshold digital circuit operation of the ratio of PMOS and NMOS current in a given process. We define the concept of process balance/imbalance as describing this ratio and explain the impact ofdifferent circuit and environmental parameters on processbalance. Many of these characteristics are best understood by the degree to which they increase or further decrease process balance. We also propose a model that provides accurate estimation of the effects of process balance that is useful for understanding the impact of process variations and the appropriate types of circuits to use for sub-threshold operation in a given process.

SUMMARY: VISDA (Visual Statistical Data Analyzer) is a caBIG analytical tool for cluster modeling, visualization and discovery that has met silver-level compatibility under the caBIG initiative. Being statistically principled and visually interfaced, VISDA exploits both hierarchical statistics modeling and human gift for pattern recognition to allow a progressive yet interactive discovery of hidden clusters within high dimensional and complex biomedical datasets. The distinctive features of VISDA are particularly useful for users across the cancer research and broader research communities to analyze complex biological data. AVAILABILITY: http://gforge.nci.nih.gov/projects/visda/

Abstract Current-mode approach in register file has the great advantage of high operation speed with low power consumption. Under 0.35- m m CMOS technology, we present a 1.85-ns read access, 32 · 32-bit, five-port register file in which a modified current-sense amplifier is used. The delay match circuit and TSPC-FF are also used to improve speed. Energy saving is achieved by current mode and other key ideas. Simulation results show it consumes 640mW at 500MHz 3.3V. It can still work at 2.3V with 350MHz 300mW. I.