Michael Penner

dblp:30/2466 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2004
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%
Theoretical computer science
1 paper
Graph algorithms and graph theory · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › cache
cache-oblivious algorithms
0.012004
Optimizing Graph Algorithms for Improved Cache Performance · IEEE Trans. Parallel Distributed Syst. 2004
Memory systems › cache
cache performance
0.012004
Optimizing Graph Algorithms for Improved Cache Performance · IEEE Trans. Parallel Distributed Syst. 2004
Graph algorithms and graph theory
graph algorithms
0.012004
Optimizing Graph Algorithms for Improved Cache Performance · IEEE Trans. Parallel Distributed Syst. 2004
Graph algorithms and graph theory
shortest path
0.012004
Optimizing Graph Algorithms for Improved Cache Performance · IEEE Trans. Parallel Distributed Syst. 2004
Memory systems
memory hierarchy
0.012004
Optimizing Graph Algorithms for Improved Cache Performance · IEEE Trans. Parallel Distributed Syst. 2004

Methods — techniques the papers use, named apart from their topics

cache-oblivious implementation · 0.1adjacency arrays · 0.1
YearPublicationVenuePosition
2004 Optimizing Graph Algorithms for Improved Cache Performance
abstract
We develop algorithmic optimizations to improve the cache performance of four fundamental graph algorithms. We present a cache-oblivious implementation of the Floyd-Warshall algorithm for the fundamental graph problem of all-pairs shortest paths by relaxing some dependencies in the iterative version. We show that this implementation achieves the lower bound on processor-memory traffic of /spl Omega/(N/sup 3///spl radic/C), where N and C are the problem size and cache size, respectively. Experimental results show that this cache-oblivious implementation shows more than six times the improvement in real execution time over that of the iterative implementation with the usual row major data layout, on three state-of-the-art architectures. Second, we address Dijkstra's algorithm for the single-source shortest paths problem and Prim's algorithm for minimum spanning tree problem. For these algorithms, we demonstrate up to two times the improvement in real execution time by using a simple cache-friendly graph representation, namely adjacency arrays. Finally, we address the matching algorithm for bipartite graphs. We show performance improvements of two to three times in real execution time by using the technique of making the algorithm initially work on subproblems to generate a suboptimal solution and, then, solving the whole problem using the suboptimal solution as a starting point. Experimental results are shown for the Pentium III, UltraSPARC III, Alpha 21264, and MIPS R12000 machines.
Joon-Sang Park, Michael Penner, Viktor Prasanna 0001
IEEE Trans. Parallel Distributed Syst.2