Future wireless communication systems require efficient and flexible baseband receivers. Meaningful efficiency metrics are key for design space exploration to quantify the algorithmic and the implementation complexity of a receiver. Most of the current established efficiency metrics are based on counting operations, thus neglecting important issues like data and storage complexity. In this paper we introduce suitable energy and area efficiency metrics which resolve the afore-mentioned disadvantages. These are decoded information bit per energy and throughput per area unit. Efficiency metrics are assessed by various implementations of turbo decoders, LDPC decoders and convolutional decoders. An exploration approach is presented, which permit an appropriate benchmarking of implementation efficiency, communications performance, and flexibility trade-offs. Two case studies demonstrate this approach and show that design space exploration should result in various efficiency evaluations rather than a single snapshot metric as done often in state-of-the-art approaches.

For binary linear codes with short and medium block length ML decoding can be achieved by solving the associated integer programming (IP) problem with a general purpose solver. IP also offers algorithms for computing the minimum distance. In this article, we present several IP formulations and computationally compare them on various LDPC and BCH codes. Most of these formulations are obtained by forcing integrality on linear programming (LP) decoding formulations proposed in the literature.

Maximum likelihood (ML) decoding is the optimal decoding algorithm for arbitrary linear block codes and can be written as an integer programming (IP) problem. Feldman relaxed this IP problem and presented linear programming (LP) based decoding. In this paper, we propose a new separation algorithm to improve the error-correcting performance of LP decoding for binary linear block codes. We use an IP formulation with indicator variables that help in detecting the violated parity checks. We derive Gomory cuts from the IP and use them in our separation algorithm. An efficient method of finding cuts induced by redundant parity checks (RPC) is also proposed. Under certain circumstances we can guarantee that these RPC cuts are valid and cut off the fractional optimal solutions of LP decoding. It is demonstrated on three LDPC codes and two BCH codes that our separation algorithm performs significantly better than LP decoding and belief propagation (BP) decoding.

In this paper a programmable Forward Error Correction (FEC) IP for a DVB-S2 receiver is presented. It is composed of a Low-Density Parity Check (LDPC), a Bose-Chaudhuri-Hoquenghem (BCH) decoder, and pre- and postprocessing units. Special emphasis is put on LDPC decoding, since it accounts for the most complexity of the IP core by far. We propose a highly efficient LDPC decoder which applies Gauss-Seidel decoding. In contrast to previous publications, we show in detail how to solve the well known problem of superpositions of permutation matrices. The enhanced convergence speed of Gauss-Seidel decoding is used to reduce area and power consumption. Furthermore, we propose a modified version of the lambda-Min algorithm which allows to further decrease the memory requirements of the decoder by compressing the extrinsic information. Compared to the latest published DVB-S2 LDPC decoders, we could reduce the clock frequency by 40% and the memory consumption by 16%, yielding large energy and area savings while offering the same throughput.

Multiple antenna systems are promising approaches to increase the data rate of wireless communication systems. There, modulated symbols are multiplexed on multiple transmission antennas. Typically an outer error correcting code is used additionally to ensure a desired quality of service for a given data rate. An appropriate communications performance can be achieved by iterative decoding, where probabilistic information are exchanged between outer decoder and the MIMO demodulator. However, in this case the MIMO demodulator has to calculate probabilistic soft-output values for each bit which can be very complex. In this paper we present a new class of linear block codes named low-density MIMO codes which reduces the complexity of the MIMO soft-demodulator and the outer channel decoder inherently by code design without decreasing the data rate of the overall system. These LDMC codes can have a better communications performance then state of the art solutions with a order of magnitude smaller decoding complexity.

We study an integer programming (IP) based separation approach to find the maximum likelihood (ML) codeword for binary linear codes. An algorithm introduced in Tanatmis et al. is extended and improved with respect to decoding performance without increasing the worst case complexity. This is demonstrated on the LDPC and the BCH code classes. Moreover, we propose an integer programming formulation to calculate the minimum distance of a binary linear code. We exemplarily compute the minimum distance of the (204, 102) LDPC code and the (576, 288) WIMAX code. Using the minimum distance of a code, a new class of valid inequalities is introduced.

Bit interleaved coded modulation (BICM) is a pragmatic approach to achieve power and bandwidth efficient transmission. At this low-density parity-check codes (LDPCC) can be utilized which are then concatenated with a modulator. The concatenation of LDPCC and modulator is done via a bit interleaver which has the task to spread information. While the matched design of an optimal LDPC degree distribution with respect to a given mapping scheme is well observed it is often assumed that the probabilistic values passed from demodulator to the LDPCC decoder are independent due to the mapping interleaver. However for higher order modulations, e.g. 16-QAM or 256-QAM, more and more bits are getting correlated during the demodulation process. The connectivity of these correlated bits have to be considered during the design of the mapping interleaver with respect to the graph of the concatenated LDPC codes. In this paper, we present the design of mapping interleavers of BICM schemes utilizing LDPC codes. Simulation results show the strong influence of correlated inputs to the performance of LDPC decodes. This correlations can cause a high error floor if the mapping interleaver is not carefully designed.

This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards. A complete exploration of the design space spanning from the decoding schedules, the node processing approximations up to the top-level decoder architecture is detailed. According to this search state-of-the-art techniques for a low complexity design have been adopted in order to meet feasible high throughput decoder implementations. An analysis of the standardized codes from the decoder-aware point of view is also given, presenting, for each one, the implementation challenges (multi rates-length codes) and bottlenecks related to the complete coverage of the standards. Synthesis results on a present 65nm CMOS technology are provided on a generic decoder architecture

Current UWB systems apply convolutional codes as their channel coding scheme. For next generation systems LDPC codes are in discussion due to their outstanding communications performance. LDPC codes are already utilized in the new WiMax and WiFi standards. Thus it is reasonable to investigate these codes as candidate LDPC codes for UWB. In this paper the authors present an implementation complexity and performance comparison of LDPC decoders. We will show that it is of great advantage to design new LDPC codes which are tailored to the special latency and throughput constraints of upcoming UWB systems. This new class of LDPC codes is named ultra-sparse LDPC codes. Synthesis results of WiMax, WiFi, and U-S LDPC decoders are presented based on an enhanced 65 nm CMOS process. We show that the implementation complexity of the new U-S LDPC decoders is 55% smaller, utilizing only 0.2 mm2instead of over 0.4 mm2, while the communications performance of all observed LDPC codes are almost identical under all the considered UWB simulation conditions.

The design of future communication systems with high throughput demands will become a critical task, especially when sophisticated channel coding schemes have to be applied. LDPC codes are one of the most promising candidates because of their outstanding communications performance. One major problem for a decoder hardware realization is the huge design space composed of many interrelated parameters which enforces drastic design trade-offs. Another important issue is the need for flexibility of such systems. In this paper we illuminate this design space with special emphasis on the strong interrelations of theses parameters. Three design studies are presented to highlight the effects on a generic architecture if some parameters are constraint by a given standard, given technology, and given area constraints

The upcoming IEEE WiMax 802.16e standard, also referred to as WirelessMAN (2005), is the next step toward very high throughput wireless backbone architectures, supporting up to 500 Mbps. It features as an advanced channel coding scheme low-density parity-check codes. The decoding of LDPC codes is an iterative process, hence many data have to be exchanged between processing units within each iteration. The variety of the specified codes and the envision of different decoding schedules for different codes pose significant challenges to an LDPC decoder hardware realization. In this paper, we present to the best of our knowledge the first published LDPC decoder architecture capable to process all specified WiMax LDPC codes. Detailed synthesis and communications performance results are shown in addition

Low-density parity-check (LDPC) codes are one of the most powerful codes known today. They are decoded iteratively by a message passing algorithm. There exist many different update schemes of the exchanged messages. The major difference of all update schemes is the convergence speed, i.e. the achieved communications performance for a limited number of iterations. This paper presents a new decoding algorithm which efficiently utilizes the encoder property of linear encodable LDPC codes. The basic idea is to interpret the LDPC encoder as an encoder with puncturing unit which opens as well the door for hybrid ARQ schemes. The presented new decoding algorithm shows a faster convergence behavior than state of art decoding schemes and it results in a lower error floor

The new standard for digital video broadcast DVB-S2 features low-density parity-check (LDPC) codes as their channel coding scheme. The codes are defined for various code rates with a block size of 64800 which allows a transmission close to the theoretical limits. The decoding of LDPC is an iterative process. For DVB-S2 about 300000 messages are processed and reordered in each of the 30 iterations. These huge data processing and storage requirements are a real challenge for the decoder hardware realization, which has to fulfill the specified throughput of 255 Mbit/s for base station applications. In this paper we show, to the best of our knowledge, the first published IP LDPC decoder core for the DVB-S2 standard. We present a synthesizable IP block based on ST Microelectronics 0.13 /spl mu/m CMOS technology.

Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular repeat-accumulate (IRA) codes belong to the class of low-density parity-check (LDPC) codes and even outperform the recently introduced turbo-codes of current communication standards. The advantage of IRA codes over LDPC codes is that they come with a linear-time encoding complexity. IRA codes can be represented by a Tanner graph with arbitrary connections between nodes of given degrees. The implementation complexity of IRA decoders is dominated by the randomness of these connections. In this paper, we present a scalable partly parallel IRA decoder architecture. We present a joint graph-decoder design to parallelize IRA codes which can be efficiently processed by this decoder without any RAM access conflicts. We show design examples of these IRA codes which outperform the UMTS turbo-code by 0.2 dB.

Turbo trellis-coded modulation (TTCM) is a very promising approach for future communication systems. It combines the advantages of channel coding with multilevel signals and the powerful turbo-codes concept. In this paper we consider VLSI implementation aspects of TTCM. We show that techniques, known from binary turbo-decoders, can be applied to TTCM to reduce the implementation complexity significantly. In detail we explore iteration control, quantization, scaling, and the MAP architecture using a bit-true model of an 8-state TTCM decoder.