This paper proposes a new approach to synthesize pipelined circuits with low-power consideration. We treat each output value of a combinational circuit as one state of a finite-state machine (FSM). If the output of a combinational circuit transits mainly among some few states, we could extract those states (output) and the corresponding input to build a subcircuit. After bipartitioning the circuit, we apply the encoding technique to the highly active subcircuit for further power reduction. In this paper, we formulate the bipartition problem and present a probabilistic-driven algorithm to bipartition a circuit so as to minimize the power dissipation. Our experimental results show that an average power reduction on several Microelectronic Center of North Carolina (MCNC) benchmarks of 31.6% is achievable.

Proposes a new bipartition-codec architecture that may reduce the power consumption of pipelined circuits. We treat each output value of a pipelined circuit as one state of a finite-state machine. If the output of a pipelined circuit mainly transitions among just a few states, we can partition the combinational portion of a pipelined circuit into two blocks: the one that contains the few states of high activity is small, and the other (that contains the remainder of low activity) is large. Consequently, the state transitions are confined to the small block most of the time. Then we replace the small block with a codec circuit, which consists of an encoder and a decoder, to reduce the internal switching activity of the block. The encoder minimizes the number of bit changes during state transitions; thus, the switching which propagates into the decoder is reduced considerably. We present experimental results on several MCNC benchmarks and obtain power savings of up to 63.7% by using our new architecture.

This paper describes a simple tree pattern matching algorithm for the code generator of compilers. The intermediate code (Register Transfer Language) is matched with the tree-rewriting rules of the instruction description which describes the target architecture to generate the assembly code. The hashing function is used in our system to transform a tree pattern matching problem into a simple number comparison. Compared with GNU C compiler (gcc), the tree pattern matching time can be reduced by 69% and the compiler time by 6%, and the space of the instruction descriptions can be reduced by 4.10 times on DLX and 2.14 on SPARC. The size of table, which is necessary for the code generator, is quite small in our method.