Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
EDBT 2026 Demo / reviewers in the wild / expert

Randall J. Brouwer

dblp:30/296 · DBLP profile ↗
← Back
3ranked-venue papers
2as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 49% Parallel and multicore computing · 36% Embedded and real-time systems · 15%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › routing
global routing		 0.021993
Task scheduling for exploiting parallelism and hierarchy in VLSI CAD algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
PHIGURE: A Parallel Hierarchical Global Router · DAC 1990
Electronic design automation
physical design		 0.021993
Task scheduling for exploiting parallelism and hierarchy in VLSI CAD algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
PHIGURE: A Parallel Hierarchical Global Router · DAC 1990
Embedded and real-time systems › real-time scheduling
dependent task scheduling		 0.011993
Task scheduling for exploiting parallelism and hierarchy in VLSI CAD algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Parallel and multicore computing
parallel programming models and scheduling		 0.011993
Task scheduling for exploiting parallelism and hierarchy in VLSI CAD algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Parallel and multicore computing
task scheduling		 0.011993
Task scheduling for exploiting parallelism and hierarchy in VLSI CAD algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Parallel and multicore computing
parallel algorithms		 0.011990
PHIGURE: A Parallel Hierarchical Global Router · DAC 1990
Parallel and multicore computing › multiprocessor system
shared-memory multiprocessor		 0.011990
PHIGURE: A Parallel Hierarchical Global Router · DAC 1990

Methods — techniques the papers use, named apart from their topics

parallelizable independent task scheduling · 0.0parallelizable dependent task scheduling · 0.0hierarchical CAD · 0.0simplex · 0.0hierarchical decomposition · 0.0
YearPublicationVenuePosition
1993 Task scheduling for exploiting parallelism and hierarchy in VLSI CAD algorithms
abstract
Two approaches to handling the computational requirements of computer-aided design problems are considered. One approach is to take advantage of the hierarchical nature of circuit design and develop hierarchical CAD algorithms. Another involves the use of parallel processing and development of parallel CAD algorithms. How these two approaches can be combined to speed up various CAD applications is discussed. Toward this goal, two general problems in scheduling are solved: parallelizable independent task scheduling (PITS) and parallelizable dependent task scheduling (PDTS). The PITS scheduling theory is applied to a parallel hierarchical circuit extractor, and the PDTS scheduling theory is applied to a parallel hierarchical global router. Both implementations show speedups of about six on eight processors of a shared-memory multiprocessor.>
Krishna P. Belkhale, Randall J. Brouwer, Prithviraj Banerjee
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
1990 PHIGURE: A Parallel Hierarchical Global Router
abstract
A new parallel hierarchical algorithm for global routing (PHIGURE) is presented. The router is based on the work of M. Burstein and R. Pelavin, (IEEE Trans. CAD, vol.CAD-2, no.4, p.223-34, Oct. 1983) but has many extensions for general global routing and parallel execution. Main features of the algorithm include structured hierarchical decomposition into separate independent tasks which are suitable for parallel execution and adaptive simplex solution for adding feedthroughs and adjusting channel heights for row-based layout. The algorithm is described and results are presented for a shared-memory multiprocessor implementation. >
Randall J. Brouwer, Prithviraj Banerjee
 DAC1
1988 A parallel simulated annealing algorithm for channel routing on a hypercube multiprocessor
abstract
The algorithm begins with an initial placement of nets in the channel using the number of tracks equal to the density of the channel. Overlapping subnets are permitted at this stage as the annealing process will gradually work to remove the overlaps. Transformations are then repeatedly applied to the channel state by moving nets around the channel in a parallel fashion. By allowing overlap situations and controlling them with appropriate cost function, the algorithm is capable of producing very good results with the advantage of decreased runtime from the parallelism. and can also be applied to extensions of the channel routing problem, such as switchbox routine with obstacle avoidance.>
Randall J. Brouwer, Prithviraj Banerjee
 ICCD1