Streaming scan test architectures can greatly optimize the test data delivery to large industrial designs. This paper discusses what happens when such architectures are combined with nearly unlimited data bandwidth provided by NVIDIA MATHS (Mechanism to Access Test-Data over High-Speed Link). There are multiple techniques for efficient use of scan bandwidth and its impact on the overall test cost and test quality. We have also architected various debug techniques for silicon bring-up. This scan architecture was designed for highest throughput to test multiple dies in parallel with lowest test power and best diagnosability.

It is realized that having a method/apparatus that accurately measures voltage noise is imperative for ATE and SLT testing to 1) reliably sign-off on production patterns; 2) effectively optimize low power settings of scan architecture; 3) screen for defects during ATE testing and apply structural patterns on SLT at desired Voltage/Frequency points; This requires optimized noise profiles and hence localized noise monitors for appropriate tuning. In addition, with NVIDIA’s chips foraying into the automotive space, functional safety has gained utmost priority, and the noise profile during In-System Test (IST) helps catch reliability and aging-related defects in the field that show up after stress and degradation. This paper proposes an enhancement to the in-system Noise Measurement macro (NMEAS) to record voltage noise during the application of structural DFT patterns, such as in ATE and SLT testing, which was not possible in the conventional noise measurement methods. The introduced technique utilizes a continuous free-running fast clock that feeds functional frequency to NMEAS during test which allows it to measure the voltage noise of the chip during both shift and capture phases. Also, a novel enable generation logic and a counter are introduced that allow for more precise characterization of the measured voltage noise data.

MATHS (Mechanism to Access Test-Data over High-Speed Link) provides a high-throughput PCIe based system to structurally test system-on-chips (SOCs) at wafer and system-level. The system removes the need for expensive test equipment by eliminating the input/output pin (IO) requirements and memory per IO needs. It simplifies the ATE architecture and design to enable smaller form factors and reduce capital costs of ownership. MATHS enables eliminating the assembly test-insertion by directly testing the SOCs on system level platforms, further reducing the costs. Since the mechanism is based on PCIe standards, it is highly portable across all platforms including ATE, system-level test, board, and in-field testing.

Safety is one of the crucial features of autonomous drive platforms, and semiconductor chips used in these architectures must guarantee functional safety aspects mandated by ISO 26262 standard. To monitor the failures due to field defects, in-system-structural-tests are automatically run during key-on and/or key-off. Upon detection of any permanent defects by the in-system-test (IST) architecture, Drive platform responds to achieve the fail-safe state of the system. In this paper, we present the IST architecture that helps with achieving highest functional safety levels on the NVIDIA Drive platform.

This paper presents the latest test methodology for NVIDIA's multi-billion transistor Mobile System on Chip (SoC) and Graphics Processing Unit (GPU). The paper describes the innovations that enhance the SoC plug-n-play scheme in terms of DFT. It also demonstrates how the architecture enables ultra-low pin count testing together with test data reuse and efficient test scheduling to improve the test quality while lowering the test cost. We present a scalable scan interface methodology coupled with core isolation and advanced clocking design while keeping the overall power budget for test within the limits of SoC Thermal Design Power (TDP). Silicon results are shared to demonstrate the effectiveness of this architecture.

Non-standardized scan interface within and across system-on-chips (SoCs) limits test-data reuse for intellectual properties (IPs). To overcome this limitation, we present a flexible and dynamic scan interface architecture that enables reuse of test-data for a given IP across SoCs with different scan pin configurations. The dynamic nature of this architecture also enables variable shift frequencies across different IPs in a given SoC. The architecture decouples the scan pin requirements from the design cycle of the IPs. It also uses bidirectional scan pins to further reduce test cost by using as few as two pins.

Interdependence of the clocking architecture across IPs and overall peak power consumption is a major bottleneck that prevents concurrent yet independent testing of an IP at a higher clock frequency. We use a dynamic clocking architecture that eliminates these dependencies and reduces peak shift power by using clock phase staggering at a granular level during system-on-chip (SoC) testing. A SoC design is typically composed of several Intellectual Property (IPs), some of which may be replicated. Generating a full set of test patterns targeting all IPs at the same time is computationally intensive and may be constrained by project schedule. Using this architecture, production test patterns are generated independently at the IP level and applied concurrently at the SoC level without exceeding the power budget of the chip during test. We present various aspects of the clocking architecture design along with simulation and silicon results to highlight the effectiveness of this architecture.

The population of small-delay defects (SDDs) in integrated circuits increases significantly as technology scales to 65 nm and below. Therefore, testing for SDDs is necessary to ensure the quality and reliability of high-performance integrated circuits fabricated with the latest technologies. Commercial timing-aware automatic test pattern generation (ATPG) tools have been developed for SDD detection. However, they only use static timing analysis reports in the form of standard delay format for path-length calculation and neglect important underlying causes, such as process variations, crosstalk, and power-supply noise, which can also induce small delays into the circuit and impact the timing of targeted paths. In this paper, we present an efficient pattern evaluation and selection procedure for screening SDDs that are caused by physical defects and by delays added to paths by process variations and crosstalk. In this procedure, the best patterns for SDDs are selected from a large repository test set. Experimental results demonstrate that our method sensitizes more LPs, detects more SDDs with a much smaller pattern count, and needs less CPU runtime compared with a commercial timing-aware ATPG tool.

Advances in the chip manufacturing process impose new requirements for post-production test. Small Delay Defects (SDDs) have become a serious problem during chip testing. Timing-aware ATPG is typically used to generate tests for this kind of defects. Here, the faults are detected through the longest path. In this paper, a novel timing-aware ATPG approach is proposed which is based on Pseudo-Boolean Optimization (PBO) in order to leverage the recent advances in solving techniques in this field. Additionally, the PBO-based approach is able to cope with the generation of hazard-free robust tests by extending the problem formulation. As a result, the faults are detected through the longest robustly testable path, i.e. independently from other delay faults. Experimental results show that a hazard-free robust test can be efficiently found for most testable timing-critical faults without much reduction in path length.

Testing for small-delay defects (SDDs) becomes necessary as technology further scales. Traditional timing-unaware transition-delay fault (TDF) ATPGs are not adequate for detecting SDDs due to sensitization of short paths. Timing-aware ATPGs suffer from multiple paths sensitization limitation and significant test cost. In this paper, we present a critical fault-based methodology to generate high-quality SDD patterns. By focusing on critical faults, high quality original pattern repository could be generated applicably with n-detect ATPG. Novel pattern evaluation and selection method is presented to further minimize pattern count while maintaining the SDD detection ability. Finally, top-off ATPG is performed to ensure meeting the target fault coverage. Experimental results demonstrate that the proposed critical fault-based method improves long path sensitization efficiency by 2.5X and saves approximately 80% CPU runtime compared with total fault-based method. Comparing with timing-aware ATPG, our pattern set detects equivalent or even more SDDs with significantly reduced pattern count.

For sub-nanometer designs, testing for small-delay defects (SDDs) is essential to achieve low defect escapes for the manufactured silicon. Existing solutions for testing SDDs are not practical for high-volume production environments due to large pattern count or long compute time, or both. In this paper, we present a production-friendly method that takes the circuit topology into account while generating patterns for SDDs. Experimental results on several IWLS'05 benchmark and six industrial circuits show that compared to the default timing-aware pattern set, the proposed method reduces pattern count an average of 172% for IWLS benchmarks and an average of 105% for industrial circuits. We demonstrate the production-worthiness of our approach by using several quality metrics and showing that the proposed method provides similar or higher coverage for SDDs compared to the default timing-aware ATPG, but only with a significantly small number of test patterns and in significantly small run time.

Testing for small-delay defects (SDDs) is necessary for ensuring product quality in smaller technology nodes. Current tools such as transition-delay fault (TDF) ATPGs and timing-aware ATPGs are either inefficient in detecting SDDs or suffering from large pattern count and CPU runtime. Furthermore, none of these methodologies take into account the impact of pattern-induced noises, e.g., power supply noise (PSN) and cross talk, which are potential sources of SDDs. In this paper, we present a hybrid method considering the impacts of pattern-induced noises to grade and select the most effective patterns for detecting SDDs. The grading procedure is performed on a large repository of patterns generated by ¿-detect TDF ATPG. Top-off ATPG is performed after pattern selection to achieve the same fault coverage as that for timing-aware ATPG. The experimental results demonstrate the efficiency of our proposed method, it results in a pattern count close to 1-detect ATPG while sensitizes similar or greater number of long paths than the commercial timing-aware ATPG pattern set.

Testing for small-delay defects (SDDs) is necessary to ensure the quality and reliability of high-performance integrated circuits fabricated with the latest technologies. These timing defects can be caused by process variations, crosstalk, and power-supply noise, as well as by physical defects such as resistive opens and shorts. Timing-aware ATPG tools have been developed for SDD detection. However, they only use static timing analysis reports for path-length calculation and neglect important parameters such as process variations, crosstalk, and power-supply noise, which can induce small delays into the circuit and impact the timing of targeted paths. In this paper, we present an efficient pattern evaluation and selection procedure for screening SDDs that are caused by physical defects and by delays added to paths by process variations and crosstalk. In this procedure, the best patterns for SDDs are selected from a large repository test set. Experimental results demonstrate that our method sensitizes more long paths and detects more SDDs with a much smaller pattern count compared with a commercial timing-aware ATPG tool.

Functional test sequences play an important role in manufacturing test for targeting defects that are not detected by structural test. In practice, functional tests are often derived from existing design-verification test sequences and they suffer from low defect coverage. Therefore, there is a need to increase their effectiveness using design-for-testability (DFT) techniques. We present a non-scan DFT technique at the register-transfer (RT) level that tackles the above problem in three steps. It can be used to increase the defect coverage for scan-based designs by making functional test sequences more effective in native (non-scan) mode. The proposed method selects a small set of control points, and through an efficient branch-and-bound strategy, determines an effective set of truth assignments to these control points (also called test modes). The original functional test is expanded by applying the same functional test sequence once with each selected test mode. Finally, a small set of state elements are chosen as observation points from the transitive fanout cone of the control points based on the number of recorded transitions. The proposed DFT method is evaluated in terms of the unmodeled defect coverage, and we introduce a new surrogate metric, called multi-segment long path sensitization, for the purpose of evaluation. Experimental results for the ITC'99 benchmark circuits, the Open RISC 1200 SoC benchmark, and the Scheduler module of the Illinois Verilog Model (IVM) show that the proposed non-scan DFT technique offers significant potential for ramping up the defect coverage of existing functional test sequences.

There is an ever-increasing demand for higher performance microprocessors within a given power budget. This demand forces design choices - that were once seen only in high-speed custom blocks - to spread throughout the microprocessor core. These unique design structures, combined with the nanometer technology test challenges such as crosstalk, process variations, power-supply noise, and resistive short and open defects, lead to unique test challenges for today's high-performance microprocessor core. In this paper, we present the scan architecture-related design-for-test (DFT) features and corresponding verification strategies of the nextgeneration Advanced Micro Devices (AMD) high-performance microprocessor core.

Small-delay defects (SDDs) have become a major concern in nanometer technology designs. Traditional timing-unaware transition-delay fault (TDF) ATPGs are not efficient in detecting SDDs since they tend to detect delay faults via shorter paths. Timing-aware ATPG tools have been proven to result in significantly large CPU runtime and pattern count. In this paper, we present a hybrid procedure that grades patterns in terms of their effectiveness in detecting SDDs and selects the most effective ones. The grading procedure is performed on a large repository of patterns generated by n-detect TDF ATPG and takes advantage of n-detect capability in detecting a delay fault n times from different paths. 1-detect TDF ATPG is performed after pattern grading and selection to ensure same fault coverage as timingaware ATPG's is obtained. Experimental results demonstrate that our proposed hybrid method is fast and efficient; it can sensitize a greater number of longer paths with much lower pattern count and CPU runtime compared to a commercial timing-aware ATPG tool.

Timing-related defects are major contributors to test escapes and in-field reliability problems for very-deep submicrometer integrated circuits. Small delay variations induced by crosstalk, process variations, power-supply noise, as well as resistive opens and shorts can potentially cause timing failures in a design, thereby leading to quality and reliability concerns. We present a test-grading technique that uses the method of output deviations for screening small-delay defects (SDDs). A new gate-delay defect probability measure is defined to model delay variations for nanometer technologies. The proposed technique intelligently selects the best set of patterns for SDD detection from ann-detect pattern set generated using timing-unaware automatic test-pattern generation (ATPG). It offers significantly lower computational complexity and excites a larger number of long paths compared to a current generation commercial timing-aware ATPG tool. Our results also show that, for the same pattern count, the selected patterns provide more effective coverage ramp-up than timing-aware ATPG and a recent pattern-selection method for random SDDs potentially caused by resistive shorts, resistive opens, and process variations.

Test data volume and test application time are major concerns for large industrial circuits. In recent years, many compression techniques have been proposed and evaluated using industrial designs. However, these methods do not target sequence- or timing-dependent failures while compressing the test patterns. Timing-related failures in high-performance integrated circuits are now increasingly dominated by small-delay defects (SDDs). We present a SDD-aware seed-selection technique for LFSR-reseeding-based test compression. Experimental results show that significant test-pattern-quality increase can be achieved when seeds are selected to target SDDs.

Timing-related failures in high-performance integrated circuits are being increasingly dominated by small-delay defects (SDDs). Such delay faults are caused by process variations, crosstalk, power-supply noise, and defects such as resistive shorts and opens. Recently, the concept of output deviations has been presented as a surrogate long-path coverage metric for SDDs. However, this approach is focused only on delay variations for logic gates and it ignores chip layout, interconnect defects, and delay variations on interconnects. We present a layout-aware output deviations metric that can easily handle interconnect delay variations. Experimental results show that interconnect-delay variations can have a significant impact on the long paths that must be targeted for the detection of SDDs. For the same pattern count, the proposed pattern-grading and pattern-selection method is more effective than a commercial timing-aware ATPG tool for SDDs, and requires considerably less CPU time.

Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, power-supply noise, as well as resistive opens and shorts can potentially cause timing failures in a design, thereby leading to quality and reliability concerns. We present a test-grading technique to leverage the method of output deviations for screening small-delay defects (SDDs). A new gate-delay defect probability measure is defined to model delay variations for nanometer technologies. The proposed technique intelligently selects the best set of patterns for SDD detection from an n-detect pattern set generated using timing-unaware automatic test-pattern generation (ATPG). It offers significantly lower computational complexity and it excites a larger number of long paths compared to previously proposed timing-aware ATPG methods. We show that, for the same pattern count, the selected patterns are more effective than timing-aware ATPG for detecting small delay defects caused by resistive shorts, resistive opens, and process variations.

This paper addresses the run-time diagnosis of delay faults in functional units of microprocessors. Despite the popularity of the stuck-at fault model, it is no longer the only relevant fault model. The delay fault model - which assumes that the faulty circuit element gets the correct value but that this value arrives too late - encompasses many of the actual in-field wearout faults in modern microprocessors. In-field wearout faults, such as time-dependent dielectric breakdown and electromigration, cause signal propagation delays which may be missed during production test time. These defects progress exponentially over time, potentially causing a catastrophic failure. Our goal is to diagnose hard delay faults (i.e., identify them as hard faults, not transients) during run-time before they lead to catastrophic chip failures. Results show that we can diagnose all injected delay faults and that prior diagnosis mechanisms, which target only stuck-at faults, miss the majority of them.

In this paper, we propose a low-cost fault tolerance technique for microprocessor multipliers, both non-pipelined (NP) and pipelined (P). Our fault tolerant multiplier designs are capable of detecting and correcting errors, diagnosing hard faults, and reconfiguring to take the faulty sub-unit off-line. We utilize the branch misprediction recovery mechanism in the microprocessor core to take the error detection process off the critical path. Our analysis shows that our scheme provides 99% fault security and, compared to a baseline unprotected multiplier, achieves this fault tolerance with low performance overhead (5% for NP and 2.5% for P multiplier) and reasonably low area (38% NP and 26% P) and power consumption (36% NP and 28.5% P) overheads