Demo Data from EDBT 2026 / reviewers in the wild / expert
P. S. Wong
dblp:30/3725
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 2018
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Databases, data management, data science and information retrieval · 2Artificial intelligence and machine learning · 1Computer networks · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 50% Integrated circuit design · 50% | |
| Computer networks
1 paper |
Internet architecture and protocols · 100% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
VLSI design |
0.0 | 1 | 1999 | A parallel embedded-processor architecture for ATM reassembly · IEEE/ACM Trans. Netw. 1999 |
Internet architecture and protocols › ATM networks
ATM adaptation layer |
0.0 | 1 | 1999 | A parallel embedded-processor architecture for ATM reassembly · IEEE/ACM Trans. Netw. 1999 |
Methods — techniques the papers use, named apart from their topics
VHDL simulation · 0.0HSPICE simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | PCA-KNN for Detection of NS1 from SERS Salivary Spectra
Nur Hainani Othman, Khuan Y. Lee, A. R. M. Radzol, Wahidah Mansor, P. S. Wong, Irene Looi |
ACIIDS (2) | 5 |
| 1999 | A parallel embedded-processor architecture for ATM reassemblyabstractThe asynchronous transfer mode (ATM) reassembly algorithm for adaptation layer five is broken down into concurrent tasks for efficient VLSI implementation. VHDL and HSPICE simulations show that the proposed reassembly chip architecture will function with ATM line rates up to 700 Mb/s. The architecture is based upon three embedded lightweight processors, a variety of supporting circuitry, and a peripheral component interface (PCI) bus host interface. An important architectural feature is the use of a paged memory management system for the reconstruction of variable length messages. Richard F. Hobson, P. S. Wong |
IEEE/ACM Trans. Netw. | 2 |
| 1995 | Solving the Tridiagonal Linear System and Poisson's Equation over a LAN-Based Computing Platform Using Distributed Shared Memory
V. Lakshmi Narasimhan, P. S. Wong |
Inf. Sci. | 2 |