Chiplet-based multi-die packages implement large numbers of inter-die interconnect bundles clustered in large micro-bump islands. These micro-bumps can be subject to manufacturing defects. The most common defect types are shorts and opens. Traditional interconnect automatic test pattern generation (I-ATPG) algorithms detect, for a given collection of interconnects, all shorts between any pair of interconnects, all open interconnects, and exclude any aliasing, independent from the interconnects’ layout positions. Exploiting knowledge of their relative layout positions, we derive a new, improved I-ATPG algorithm. For a user-defined and scalable definition of realistic shorts, the new I-ATPG approach (1) increases the defect coverage significantly (in an example case, between 18% and 67%) by including realistic inter-bundle shorts between micro-bumps from adjacent bundles, and (2) reduces the overall test pattern count (and hence, the resulting test time) by 33% by providing test patterns for realistic shorts only.

Chip manufacturers and hyperscalers are becoming increasingly aware of the problem posed by Silent Data Errors (SDE) and are taking steps to address it. Major computing facilities operators like Meta and Google have emphasized the critical role of SDEs in today’s microprocessors. Numerous studies in the literature have highlighted the severity of this issue, especially in datacenter applications operating at large scales. These errors can lead to data loss and require a significant amount of time and effort to resolve through debugging engineering efforts, which can take months to complete. In this paper, we provide an overview of the issue of SDEs, including an explanation of the problem and the current methods used to address it, as well as gaps that still exist in addressing the issue. We also discuss the different sources of SDEs, including post-manufacturing testing failures, voltage and timing marginalities, and hard-to-detect faults. The paper emphasizes the impact of timing marginalities as a significant source of SDEs. Finally, our spotlight points to the architecture and system dimensions of the problem: we describe the challenges of measuring the true (still unknown) rates of SDE from CPUs, and emphasize on the role of detailed microarchitectural simulation models for this purpose. We present data on the severity of SDEs and their predicted rates under various operating conditions, sources of faults, and technology fabrication nodes.

This IP session will consist of three presentations. A summary of each presentation is given below.

Yield considerations led to die-disaggregation. Implementing complex functions on an SoC led to functional partitioning. These trends have spurred the need for integrating heterogeneous chip-lets from multiple fab vendors, using proprietary interconnect technology. Chip-let interconnects must be thoroughly tested, post packaging, to guarantee correct SoC functionality. This paper argues for the need to standardize test requirements for chip-let interconnects and features to be incorporated into such a standard. This can be part of IEEE 1838 standard for chip-let testing.

Many semi-conductor manufacturing companies use 3D interconnect technology to flexibly combine smaller heterogeneous designs in a system-on-package. Internal I/O (IIO) are placed at two ends of the inter-die interconnect. Small dimension of IIOs prohibits tester probing. This, along with the very large number of inter-die interconnects poses a serious challenge to robustly test these interconnects. This is a hindrance to adopting 3D interconnect technologies. This paper discusses the difference between IIO testing and GPIO, HSIO testing. A novel IIO BIST solution, which removes a major obstacle for adopting 3D-interconnect technology, is presented.

A comparative study of pre-bond TSV test methodologies is presented in this paper. The study includes the impact of interconnect wires and I/O transmitter and receiver parameters on the sensitivities of the test methods. We study four classes of test methods. Simulation results provided show that two classes, ring-oscillator based [7], [8] and pulse-shrinking based method [15], are insensitive to open and short defects. We also show that there is a trade-off in using the other two methods. The sense-amplifier based method [12], [13], [19] is sensitive to open defects. However, it has limited sensitivity to leakage defects and has limitations in its use for high speed I/Os. On the other hand the pulse counting method [18], [14] is sensitive to both open and leakage defects and can be used for high speed I/Os, However, it consumes more power and requires more time for tests than the sense-amplifier based method. These results can be leveraged to identify usage guidelines for these methods.

Prebond TSV testing is a powerful technique to identify faulty TSVs prior to 3-D stacking and to boost up the chip yield rate significantly. Existing prebond test methodologies experience fault detection resolution challenges, large implementation overheads, and most importantly, wide performance fluctuations in presence of process corners, supply voltage, temperature (PVT) variations. In this work, we propose a no-touch TSV test methodology that is resilient against PVT variations, or test environment parameters, thus suitable for industry practical uses. The proposed methodology is based on the idea of charging the TSV RC-network and counting the number of voltage pulses required to charge up the TSV. We undertake a detailed performance evaluation of the test methodology by adopting state-of-the-art industry technology parameters. The major advantage of the test methodology is its strong resilience to PVT variations and simplicity of implementation. In addition, a DFT circuitry is proposed to share among a group of TSVs to lower the design overhead.

In this IP session, there will be 3 presentations focusing on the state-of-the-art memory test practices from tools and industrial implementation perspectives. The 1stpresentation will discuss the memory test strategies in the automotive space. The 2ndpresentation discusses memory tests strategies for enabling test cost reduction. The 3rdpresentation will discuss on array BIST and its presence and usage in various applications of the current generation designs.

In this IP session, there will be 3 presentations focusing on functional testing and fault injection for automotive functional safety applications as well as a discussion on fault simulation and modeling for relevant analog test content. The 1stpresentation will discuss verification solutions that accelerate fault injection for diagnostic coverage to meet ASIL requirements. The 2ndpresentation discusses the use of focused random testing to achieve better functional coverage for automotive products. The 3rdpresentation will discuss the various challenges associated with analog fault coverage in the absence of standards and discusses approaches to address them.

Start of the above-titled section of the conference proceedings record.

This paper presents silicon results for two such proposed fault models: the cell aware fault model and the small delay defect fault model. The corresponding tests including cell-aware ATPG tests and Fast-than at-speed TDF tests are evaluated on an industrial design. Results from a high volume manufacturing experiment on a 65nm Serial Attached SCSI (SAS) RAID-On-a-Chip (ROC) device are presented. The incremental value of these fault models and tests beyond our current test flow is discussed.

Use of Nand Flash memory in storage devices is increasing at an exponential rate. As the technology feature size shrink, the reliability and endurance for the Nand device reduces. Currently Nand devices can have more than 258Gb cells. Testing such devices is not a trivial proposition. In this presentation we will discuss the failure modes for Nand flash, the test methods used and the challenges that we face.

Due to high switching activities in test mode, circuit power consumption is higher than its functional operation. Large switching in the circuit during launch-to-capture cycles not only negatively impacts circuit performance causing overkill, but could also burn tester probes during wafer test due to the excessive current they must drive. It is necessary to develop a quick and effective method for evaluating each pattern, identifing high-power patterns considering functional and tester probes' current limits and making the final pattern set power-safe. Compared with previous low-power methods that deal with scan structure modification or pattern filling techniques, the new proposed method takes into account layout information and resistance in the power distribution network and can identify peak current among C4 power bumps. Post-processing steps replace power-unsafe patterns with low-power ones. The final pattern set provides considerable peak current reduction while fault coverage is maintained.

Researchers, based primarily on theoretical analysis of different coverage metric, have proposed the need to cover small delay defect (SDD). There is very little silicon data justifying the need to add SDD tests to the manufacturing flow. This paper attempts to fill this gap. A high volume manufacturing experiment to ascertain the added screening capability of defective parts and infant mortality of FAST_TDF tests are described. Quantitative silicon data are presented.

Existing commercial power sign-off tools analyze the functional mode of operation for a small time window. The detailed analysis used makes such tools impractical in determining test peak power where a large amount of scan shift cycles have to be analyzed. This paper proposes an approximate test peak power analysis flow capable of computing test peak power at each power bump in the design. The flow uses physical design information, like power grid, power bump location, packaging information, along with the design netlist. We present correlation studies, on industrial design, and show the proposed flow to correlate within 5%of the accurate commercial power sign-off tool. In addition, we demonstrate that this flow, unlike the commercial power sign-off tool, can process a very large number of transition delay tests in a reasonable time.

Speed binning groups ICs with similar performance and price point. Die matching matches dice with similar performance for system and 3D integration. A hybrid test flow combining process monitor readings and search using manufacturing test is presenteds. This flow eliminates error due to process monitor data inaccuracies and reduces test time of manufacturing test based search. Silicon data is presented.

A technique to optimize power determines the minimum operating voltage during manufacturing testing on a per die basis. The die is then programmed to operate at the minimum voltage for the life of the die. Silicon results to evaluate the effectiveness of a variety of techniques to determine the minimum voltage of a die, in a manufacturing environment, are presented. Based on this we propose an adaptive hybrid test flow that is guaranteed to compute the minimum voltage while minimizing test time. Finally, sample data on power optimization achievable using power reduction is provided.

Freezing scan cell outputs can block transitions to the combinational components thus reduce shift power. The extra logic introduces area overhead, reduces timing margin and increases power in capture mode. This paper proposes a partial gating flow that calculates instance toggling probability to identify power sensitive cells. The toggling rate reduction tendency is demonstrated to be useful in estimating how much extra logic is needed to achieve a desired shift power reduction rate for a design. To ensure power safety across entire test session, the toggling rate metric is enhanced to consider the effect of capture power increase. A complementary pair of weights can adjust the power change in shift and capture modes, thus achieve an overall balanced power safety. The toggling probability metric along with the proposed flow provide a flexibility that benefits various practical power requirements when considering current limits of both circuit and tester.

Scanning of test vectors during testing causes unnecessary and excessive switching in the combinational circuit compared to that in the normal operation. In this paper, we propose a modified design of a scan flip-flop which eliminates the power consumed due to unnecessary switching in the combinational circuit during scan shift, with a little impact on performance. The new scan flip-flop disables the slave latch during scan, and uses an alternate low cost dynamic latch in the scan path instead. Methods for generating slave latch disable control signal are also presented.

Large switching during launch-to-capture cycle in delay test not only negatively impacts circuit performance causing overkill, but could also burn tester probes due to the excessive current they must drive. It is necessary to develop a quick and effective method to evaluate each pattern, identify high-power ones considering functional and tester probes' current limit and make the final pattern set power-safe. Compared with previous low-power methods that deal with scan structure modification or pattern filling techniques, the new proposed method takes into account layout information and resistance in power distribution network and can identify peak current among C4 power bumps. Post-processing steps replace power-unsafe patterns with low-power ones. The final pattern set provides considerable peak current reduction while fault coverage is maintained.

Latch based arrays are commonly used as small embedded memories. There are often a large number of such memories in a design. Due to the large area overhead of memory BISTs, scan is often used to test such memories. In this paper we show that with a minor modification of a marching sequence targeting only the transition delay faults at the latch boundaries, a comprehensive set of faults can be detected. The comprehensive fault set includes all stuck-at, stuck-open and bridging faults inside a cell of the array as well as all inter-cell bridging faults. This test set also includes a retention test for such memories.

The integration of on-chip monitors that monitor a variety of chip parameters like temperature; process corner, etc. are finding increasing use in modern day SOCs and Microprocessors. Such monitors are used for optimizing various performance measures as well as for device characterization. With newer processes the challenge is of designing reliable ICs from inherently unreliable components. More specifically designers have to address the issue of extreme process variation and time-dependent aging. New on-chip design techniques to characterize the manufacturing and time-dependent variation sources of a chip have been proposed. This special session will present three papers dealing with this topic. The first will discuss test structures for characterizing variations in narrow-width devices that adversely affect SRAM reliability. Application of variation characterization to post-silicon repair of SRAM will be presented along with silicon results from test chips. The second paper will discuss a number of “silicon odometer” designs that we have implemented in order to measure circuit degradation caused by front-end-of-line reliability mechanisms such as Hot Carrier Injection (HCI), Bias Temperature Instability (BTI), and Time Dependent Dielectric Breakdown (TDDB). The third paper will present silicon results from a 90nm and 65nm production design that tries to ascertain the accuracy of on-chip monitors in current designs vis-à-vis more direct measurement techniques like manufacturing testing. An analysis of the results for using on-chip monitors to match dies for 3D-applications or system integration will be presented.

Multiple input switching (MIS) on off-path inputs is known to increase the delay through a gate. However, due to the complexity of incorporating MIS in timing analysis, design flows typically ignore the effect of MIS. Test tools also do not attempt to maximize the off-path switching to maximize delays through a path. In this paper we study the impact of not maximizing the switching on the off-path inputs in different process corners. We present quantitative data to estimate the test escape or mis-binning that could result if MIS is not considered as part of our path-delay test generation process.

This paper presents a novel path selection methodology to select paths for monitoring unexpected systematic timing effects. The methodology consists of three components: path filtering, path encoding, and path clustering. Given a large set of critical paths, in path filtering, the goal is to filter out paths that cannot be functionally sensitized. To explore the space of unexpected timing effects, a set of features are defined to encode paths into path vectors. Each feature is a source of concern that may potentially contribute to the cause of an unexpected timing effect. Finally, a kernel-based clustering algorithm is employed to group similar path vectors into clusters from which the best representative paths are selected for post-silicon monitoring. The effectiveness of our proposed methodology is demonstrated through experiments on an industrial ASIC design.

Scan chains contain a high percentage of the transistors in logic parts of VLSI designs. Nevertheless, faults inside scan cells are not directly targeted by scan based tests currently used, and they are assumed to be detected by what are called flush tests. Recently we investigated the detectability of stuck-at, stuck-on and stuck-open faults internal to scan chains using existing tests. We also proposed new flush tests and appropriate ordering of flush tests to achieve higher fault coverage. In this paper, we investigate detection of a set of scan cell internal bridging faults extracted from layout. We show that the detection of some zero-resistance non-feedback bridging faults requires two-pattern tests. Half-speed flush tests we proposed earlier to improve the coverage of stuck-at, stuck-on and stuck-open faults also detect additional bridging faults. We classify the undetectable faults based on the reasons for their undetectability. We observe that the driver strengths of the scan cell inputs can be optimized to improve the bridging fault coverage. Both zero-resistance and nonzero-resistance bridging fault models are considered in this work. A low power supply voltage based test method and IDDQ testing are examined for resistive bridging fault detection.

A digital circuit usually comprises a controller and datapath. The time spent for determining a valid controller behavior to detect a fault usually dominates test generation time. A validation test set is used to verify controller behavior and, hence, it activates various controller behaviors. In this paper, we present a novel methodology wherein the controller behaviors exercised by test sequences in a validation test set are reused for detecting faults in the datapath. A heuristic is used to identify controller behaviors that can justify/propagate pre-computed test vectors/responses of datapath register-transfer level (RTL) modules. Such controller behaviors are said to becompatiblewith the corresponding precomputed test vectors/responses. The heuristic is fairly accurate, resulting in the detection of a majority of stuck-at faults in the datapath RTL modules. Also, since test generation is performed at the RTL and the controller behavior is predetermined, test generation time is reduced. For microprocessors, if the validation test set consists of instruction sequences then the proposed methodology also generates instruction-level test sequences.

We show that rising and falling delays in gates can differ considerably. Simulation data, using 40 nm and 65 nm process technology, shows an increasing trend and that the slow transition delay could be two times of the faster transition delay. This translates to an asymmetry between the rise and fall delays along a path. Based on this we propose refinements to the following delay test methodology: (i) selection of robust path delay tests for delay characterization; (ii) refinements to small delay defects coverage metric; and (iii) an alternative to the inline resistance fault (IRF) model for selecting TDF tests.

The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, even though such defects may affect functional operation. Existing Logic BIST structures suffer from the same limitations. A novel Logic BIST architecture to detect such defects is proposed. Unlike other sequences, like checking experiments, the enhancements are simple and independent of the circuit under test.

Nearly half of the transistors in the logic parts of large VLSI designs typically reside inside scan cells. Faults in scan cells may affect functional operation if left undetected. Such undetected faults may also affect the long term reliability of shipped products. Nevertheless, current test generation procedures do not directly target faults internal to the scan cells. Typically it is assumed that scan chain tests, called flush tests, test the scan cells sufficiently. We showed that flush tests applied at slower clock rates, called half-speed flush tests, and tests for scan cell inputs and outputs, detect stuck-at and stuck-on faults internal to scan cells to a similar extent as checking sequence based tests proposed earlier. In this work, we investigate the detection of opens in transistors internal to scan cells. A new flush test and a new method to apply flush tests are proposed to greatly enhance the coverage of opens. We also propose new scan based tests to further increase the coverage of opens. The proposed tests are shown to achieve the maximum possible coverage of opens in transistors internal to scan cells.

Sticky path-delay faults are path delay faults that are neither robustly nor non-robustly testable, but cannot be proven functionally unsensitizable. Better characterization of delay test quality requires a proper analysis of sticky path-delay faults. Furthermore, careful elimination of sticky path-delay faults contributes significantly to test development productivity and reduction of delay test cost. We present an industrial case study that shows the following, (a) On average, even after designers have removed false paths using automated tools and manual overrides, about 8% of path-delay faults with slack less than 10% of the clock period can be sticky, (b) Our approach, which extends a previously proposed technique, identifies a large subset of sticky path-delay faults that cannot cause functional failures and hence can be eliminated from further consideration. This significantly refines the delay test quality assessment and test development effort, (c) Our approach significantly reprioritizes (reorders) the remaining paths for test generation thereby improving the quality of the target path list.

Scan chains contain approximately 50% of the logic transistors in large industrial designs. Yet, faults in the scan cells are not directly targeted by scan tests and assumed detected by flush tests. Reported results of targeting the scan cell internal faults using checking sequences show such tests to be about 4.5 times longer than scan stuck-at test sets and require a sequential test generator, even for full scan circuits. We present the first step in developing an alternative test methodology for scan cell internal faults. Fault detection capability of existing tests (flush tests, stuck-at tests and transition delay fault tests) are quantified. Existing tests are shown to have similar coverage as checking sequences. A new flush test, viz. half-speed flush test, is defined. This new test is shown to add 2.3% and 8.8% to the stuck-at and stuck-on fault coverage, respectively.

This paper examines the problem of exact delay fault grading in non-scan sequential circuits using a sequence of test patterns that are applied with a rated clock. Delay faults ending at flip-flops are latched as uncorrelated errors. The errors latched on flip-flops by previous tests may enhance the at-speed delay fault coverage for each pattern in the sequence. In addition, the propagation of errors (and the faults they represent) may be facilitated by other latched errors as well as potential delayed transitions activated by each at-speed test application. An exact grading method is presented and its impact over existing methods is demonstrated experimentally

This paper presents a study of the implication based functional constraint extraction techniques to generate pseudo functional scan tests. Novel algorithms to extract pair-wise and multi-node constraints as Boolean expressions on arbitrary gates in the design are presented. Its impact on reducing the overkill in testing was analyzed, and report the trade-offs in coverage and scan-loads for a number of fault models. In the case of path-delay fault model, it was shown that the longest paths contribute most to the over-testing problem, raising the question about scan testing of the longest paths. Finally, the evaluation of the functional constraints on large industrial circuits show that the proposed constraint generation algorithm generate a powerful set of constraints most of which are not captured in the constraints extracted by designers for design-verification purposes

Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel multi-cycle path delay fault simulator. Our experiments show that path delay fault simulation run-time grows linearly with path list size. Contrary to commonly held notion that path delay fault simulation is more expensive than stuck-at fault simulation, our experiments show that performance of path delay fault grading is comparable to that of stuck-at fault grading. Finally, we propose and evaluate a heuristic that can improve path delay fault simulation performance and also aid in selection of tests for speed-limiting paths.

Logic proximity bridge (LPB) patterns were proposed as an alternative to realistic bridge and n-detect patterns based on simulation studies. Here, silicon evaluation of logic proximity bridge patterns, on a mobile chipset product, is presented. Results show these patterns to significantly increase the class scan fallout above and beyond stuck-at patterns, consisting of single load and multi-load patterns, with very high stuck-at fault coverage. In addition it points to the usefulness of generating ATPG patterns using multiple fault models, LPB faults being one of them.

A novel function-based method for error propagation is proposed for exact delay fault coverage, using a single rated clock for fault activation under any delay fault model. Sequential circuits without full scan are considered. A latched error at a flip-flop represents one or more delay faults and is allowed to propagate to an observable point with or without the support of other latched errors. Existing methods allow only one flip-flop to have an error during the propagation phase to simplify the process of error propagation at the expense of decreased fault coverage. The advantage of the proposed method is demonstrated experimentally using the path-delay-fault model with more than 20% improvement in fault coverage.

Intel's aggressive process technology, used in manufacturing high-end microprocessors, is adding to the already difficult task of meeting very low DPM targets at an acceptable cost. This talk focuses on the challenges in improving productivity and meeting DPM goals for the logic part of our design, as opposed to the cache and I/O sections. We examine the entire HVM test flow and discuss on-going work to improve logic test quality and also highlight research problems that needs solution to achieve our goal

The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across latches results in signals which propagate across multiple clock cycles along paths with multiple latches. These paths need to be tested for delay failures to ensure reliability of performance. However, many of these multi-cycle paths can be untestable and significant computational effort is wasted in targeting such paths during test generation and fault grading. To save this computational effort, a-priori identification of untestable multicycle paths is desired. We address this issue in our paper through a novel and unique framework: unlike traditional techniques, which focus only on single-cycle path delay faults (for flip-flop based designs with single clock), our framework efficiently identifies untestable multi-cycle path delay faults (Mpdfs) in latch-based designs with multiple clocks. We use a novel graphical representation and sequential implications to identify non-robustly untestable M-pdfs through a three-step methodology. Results for industrial designs demonstrate the effectiveness and scalability of our framework.

The first path implicit and exact non-robust path delay fault grading technique for non-scan sequential circuits is presented. Non enumerative exact coverage is obtained, by allowing any latched error representing a delayed transition to propagate to a primary output with the support of other potentially latched errors. The generalized error propagation is done by symbolic simulation. Appropriate data structures for function manipulation are used. The advantage of the proposed method is demonstrated experimentally with consistent improvement in coverage over an existing pessimistic heuristic despite enforced bounds on the memory requirements.

The notion of logic proximity bridge (LPB) is introduced. An algorithm to enumerate LPBs, using only the logic net-list, is discussed. Although no correlation exist between the LPB list and the realistic bridge list, LPB patterns are shown to compare very favorably with realistic bridge and n-detect patterns on several coverage metrics. This result points to the potential for LPB patterns as an alternative to both realistic bridge and n-detect patterns.

Silicon evaluation of scan patterns, targeting realistic bridges, for a high performance microprocessor is presented. The practicality of generating realistic bridge patterns is demonstrated. Silicon data, with and without functional fails, and in the presence of n-detect tests are presented. Data points to the value of and efficiency of bridge patterns. Data also shows the advantage of using supplemental bridge patterns when compared with supplemental stuck-at patterns.

The scope and need for scan based transition tests in the context of high volume manufacturing testing of microprocessors is discussed. A classification of transition faults for latch based design is presented. Finally, we discuss a silicon experiment to understand the most fundamental issue of scan based transition testing viz. their robustness.

Scan-based transition tests are added to improve the detection of speed failures in sequential circuits. Empirical data suggests that both data volume and application time will increase dramatically for such transition testing. Techniques to address the above problem for a class of transition tests, called enhanced transition tests, are proposed in this article.The first technique, which combines the proposed transition test chains with the ATE repeat capability, reduces test data volume by 46.5% when compared with transition tests computed by a commercial transition test ATPG tool. However, the test application time may sometimes increase. To address the test time issue, a new DFT technique, Exchange Scan, is proposed. Exchange scan reduces both data volume and application time by 46.5%. These techniques rely on the use of hold-scan cells and highlight the effectiveness of hold-scan design to address test time and test data volume issues. In addition, we address the problem of yield loss due to incidental overtesting of functionally-untestable transition faults, and we formulate an efficient adjustment to the algorithm to keep the overtest ratio low. Our experimental results show that up to 14.5% reduction in overtest ratio can be achieved, with an average overtest reduction of 4.68%.

Research in improving test quality has focused on identifying better fault models and coverage metrics and tools to achieve high coverage. The test generation and test application methodology is usually not considered. We attempt to understand the implication of a test generation and test application methodology, viz, partitioned testing, on product quality. In partitioned testing, patterns are applied to one part of the design while the other parts are maintained in a quiescent state. Quantitative data on several aspects of partitioned testing, using some industrial test cases, are presented. It highlights the need for generating patterns using different partition sizes, generating longer test sequences and the need to include functional testing in the test suite. In addition, we argue that a different metric is needed to evaluate functional pattern quality to cover the gaps identified.

This work presents a novel technique to identify functionally untestable transition faults in latch based designs with multiple clock domains, bringing to light unaddressed issues related to untestable fault identification in such design environments. We also introduce and provide a solution to a new variant of un-testability analysis wherein "architectural constraints'' are absorbed during the analysis. We give our tool the capability of handling transition faults resulting from defects of varying sizes, and evaluate our tool for various industrial circuits. The proposed algorithm is compared with a state-of-the-art sequential ATPG tool, and our method has shown much better performance both in the context of scan ATPG and functional test development. Results indicate that the proposed technique identifies considerably more untestable transition faults than those that can be deduced from the knowledge of untestable stuck-at faults. Additional insights from our results point to a greater need to eliminate untestable transition faults as compared to stuck-at faults, for more efficient test pattern generation and accurate coverage computation.

Enumeration and prioritization of highly probable bridges based on the circuit layout and manufacturing defect data is a key step in defect-based testing. Existing solutions either do not scale to large designs or compromise on the accuracy of the computation when applied to very large circuits. This paper presents a scalable and efficient methodology to accurately extract two-node bridges from very large circuits. To our knowledge, this is the first solution to be presented that can process such large industrial designs accurately. It also naturally addresses two important issues viz. through the cell routing and name propagation. Experimental results illustrating key features of the algorithm, including scalability and efficient memory usage, are presented.

This paper presents a novel, low cost technique based on implications to identify untestable bridging faults in sequential circuits. Sequential symbolic simulation is first performed, as a preprocessing step, to identify nets which are uncontrollable to a specific logic value. Then, an implication-based analysis is carried out for each fault to determine if a particular fault is testable or not. We also use information about the untestable stuck-at faults to filter out some bridges early in the analysis process. The application of our technique to ISCAS '89 sequential benchmark circuits and a few industrial circuits showed that a large number of untestable bridges could be identified at a low cost, both in terms of memory and execution time.

Current bridge fault extraction techniques are limited by performance and capacity constraints. In this paper, we present a fast and accurate algorithm to extract and rank two-node bridges based on the computation of their weighted critical area. Experimental results showing the algorithm's performance are presented.

An impressive body of theoretical research to model the behavior of bridges exists. We take that a step further and describe an experiment to compute single cycle scan tests for bridges and evaluate them in silicon. Experimental data, on a high volume part, shows that by marginally increasing the static bridge fault coverage of realistic bridges, unique parts missed by a comprehensive set of stuck-at tests were detected. We believe that this is the first silicon data on the value of adding single cycle scan tests for bridges to the manufacturing flow.

Scan based transition tests are added to improve the detection of IC speed failures using scan tests. Empirical data suggests that both data volume and application time for transition test will increase dramatically. Techniques to address this problem, for a class of transition tests called "enhanced transition tests", are proposed. The first technique, which combines the ATE repeat capability and the notion of transition test chains, reduces test data volume by 46.5%, when compared with transition tests computed by a commercial transition test ATPG tool. The test application time could increase or decrease. To address the test time issue, exchange scan, a new DFT technique, is proposed. Exchange scan reduces both data volume and application time by 46.5%. These techniques rely on the use of hold scan cells and highlight the effectiveness of hold-scan design to address test time and test data volume issues.

A number of new transition fault models for resistive vias and contacts in static CMOS circuits that cause speed failures are presented. The uniqueness of the new fault models are formally established. Fault simulation experiments performed on a large microprocessor show that there is no correlation between the newly proposed models and the classical fault models. Finally, we show that failures caused by bridges and opens in domino CMOS circuits require different fault models, and different test application considerations, than static CMOS circuits. It shows that there are defects that do not cause errors when tests are applied at high speed but fail when tests are applied at slow speed. This contradicts an assumption often made in speed-binning.

Previously published work has pointed out that open defects are escaping test screens. To plug this hole, tests directed at nets susceptible to opens are required, and, therefore, nets susceptible to opens need to be identified. Opens caused by random particles have been modeled using weighted critical area (WCA) and have been previously studied. Here, we present a model that abstracts a class of systematic failure mechanisms that leads to open nets. An algorithm to calculate net scores using this model is presented. Experimental results on industrial designs show the algorithm to have reasonable performance.

This article describes a diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and space efficient. The simulator represents indistinguishable classes of faults as memory efficient lists. The use of lists reduces the number of output response comparisons between faults and hence speeds up the simulation process. The lists also make it easy to drop faults when they are fully distinguished from other faults. Experimental results on the ISCAS89 circuits show that the simulator runs significantly faster than an earlier work based on distinguishability matrices, and for large circuits is faster and more memory efficient than a recent method based on lists of indistinguishable faults. The paper provides the first reports on pessimistic and optimistic diagnostic measures for all faults of the large ISCAS circuits with known deterministic tests. The diagnostic fault simulator has also been modified to diagnose defects, given the output responses of failing devices. Results on simulated bridging defects show that the diagnosis time is comparable to the time for fault simulation with fault dropping.

Given a set of memory array faults, the problem of computing a compact March test that detects all specified memory array faults is addressed. In this paper, we propose a novel approach in which every memory array fault is modeled by a set of primitive memory faults. A primitive March test is defined for each primitive memory fault. We show that March tests that detect the specified memory array faults are composed of primitive March tests. A method to compact the March tests for the specified memory array faults is described. A set of examples to illustrate the approach is presented. Experimental results demonstrate the productivity gained using the proposed framework.

Defect based testing is based on the premise that it is possible to extract high probability defects viz. bridges and opens using layout and defect data. We present a very efficient algorithm to extract two-node bridges from layout. Comparison results with a popular tool show that our algorithm is considerably faster and that it has higher capacity.

An analysis of the energy consumption ratio (ECR) test method, based on simulation study of resistive bridges and resistive opens, is presented. These defect classes comprise a very significant percentage of the defects causing speed failures. We show: (i) bridges causing delay failures and detectable by the difference I/sub DDQ/ method is detected by the ECR test method; and (ii) bridges and opens causing delay failures but not detectable by the difference I/sub DDQ/ method are also detected by the ECR test method. This highlights a very significant advantage of the ECR test method over I/sub DDQ/ test methods. The underlying reason as to why the ECR test method is good at detecting delay defects is presented. Based on that we develop a new test method called the ECR-VDD test. The usefulness of the new method in detecting delay defects is validated using simulation results.

Enumeration and prioritization of highly probable bridges based on the circuit layout and manufacturing defect data is a key step in defect based testing. Existing solutions either do not scale to large designs or compromise on the accuracy of the computation when applied to very large circuits. This paper presents a scalable and efficient methodology to accurately extract two node bridges from very large circuits. To our knowledge, this is the first solution to be presented that can process such large industrial designs accurately. It also naturally addresses two important issues viz. through the cell routing and name propagation. Experimental results illustrating key features of the algorithm, including scalability and efficient memory usage, are presented.

State-transition-based method (STBM), a fast algorithm for computing leakage fault coverage of I/sub DDQ/ tests and selecting optimal I/sub DDQ/ measurement points, targeting leakage faults, is presented. Experimental results presented show that STBM outperforms all known algorithms for the same problems. A comparative study of leakage and pseudo-stuck-at fault models, the latter used by commercial tool vendors, show that the pseudo-stuck-at coverage values are very pessimistic.

High resistance bridges (resistive bridges) are becoming more common. Such bridges cause speed failures. Published experimental results show that current tests are not good at detecting such defects. The following results, pertinent to resolving the above issue, are presented: mechanisms by which bridges cause speed failure; identification of non-classical transition tests for such bridges; and the usefulness and pitfalls of using low voltage testing to detect such bridges.

Dictionary encoding schemes have not addressed the cost of reconstructing the dictionary during fault location. We show that by modifying a previously proposed dictionary encoding scheme only small portions of the information need be reconstructed during fault location. This provides a mechanism to reduce the number of secondary accesses during fault location. For pass-fail dictionaries, we present a simplified encoding scheme that reduces both the secondary storage requirement as well as the number of secondary accesses. A novel dictionary structure, known as hybrid dictionaries, which retains the full resolution with respect to modeled faults is presented. Heuristics to compute such dictionaries, its usefulness and how such dictionaries can be encoded for quick information retrieval are discussed.

Given a set of memory array faults the problem of computing an optimal March test that detects all specified memory array faults is addressed. In this paper, we propose a novel approach in which every memory army fault is modeled by a set of primitive memory faults. A primitive March test is defined for each primitive memory fault. We show that March tests that detect the specified memory array faults are composed of primitive March tests. A method to compute the optimal March tests for the specified memory array faults is described. A set of examples to illustrate the approach is presented.

Reduction of power dissipation during test application is studied for scan designs and for combinational circuits tested using built-in self-test (BIST). The problems are shown to be intractable. Heuristics to solve these problems are discussed. We show that heuristics with good performance bounds can be derived for combinational circuits tested using BIST. Experimental results show that considerable reduction in power dissipation can be obtained using the proposed techniques.

Novel algorithms for locating bridging faults, based on the voting and wired models, in combinational circuits are presented. The algorithm uses small portions of the stuck-at fault dictionary, not the bridge fault dictionary, computed during fault location. This, along with an implicit representation of bridging faults, contributes significantly to the efficiency of the algorithm. Experimental evaluation of the algorithm on ISCAS circuits is presented.

Recent empirical and simulation studies show that adding at-speed testing to the test suite helps in detecting defective ICs missed by slow-speed and I/sub DDQ/ testing. At-speed testing attempts to detect ICs with defects, like bridges and opens, which cause faulty dynamic logic behavior. Path delay tests and transition tests are two popular tests used during at-speed testing. We show that these tests often fail to detect many bridges and opens which cause faulty dynamic behavior. Computing at speed tests is therefore fundamentally different from computing delay tests for parametric testing and new techniques need to be developed.

Reliability screens are used to reduce infant mortality. The quality of the stress test set used during. The screening process has a direct bearing on the effectiveness of the screen. We have formally studied the problem of computing good quality stress tests for some commonly occurring defects like gate-oxide shorts and interconnect defects. Methods to compute stress tests for gate-oxide defects have been discussed elsewhere. Here we present a formal study of the problem of computing stress rests for interconnect defects.

A diagnostic test generation system for computing I/sub DQQ/ diagnostic test sets for bridging faults in combinational circuits is presented. The system uses fault sampling. Experimental results presented show that fault sampling is a very effective method for computing diagnostic test sets, especially when the number of target faults is very large.

We present two algorithms, called list-based scheme and tree-based scheme, to compute bridging fault (BF) coverage ofIDDQtests. These algorithms use the novel ideal of “indistinguishable pairs,” which makes it more efficient and versatile than known fault simulation algorithms. Unlike known algorithms, the two algorithms can be used for combinational as well as sequential circuits and for arbitrary sets of BFs. Experiments show that the tree-based scheme is, in general, better than the list-based scheme. But the list-based scheme is better for some classes of faults.

The quality of diagnostic test sets (DTS) are determined using diagnostic fault simulation (DFS). We propose a novel approximation algorithm, called "EC/IC Sampling", for DFS. It samples the set of equivalence classes (EC)/indistinguishable classes (IC). An approach to sample ECs/ICs implicitly, without explicitly enumerating the set of ECs/ICs, is presented. Experimental evaluation of the proposed technique show it to be very effective.

Multilevel Logic Optimization Transformations used in existing logic synthesis systems are characterized with respect to their testability preserving and testability enhancing properties. A sufficient condition for a multilevel unate circuit to be "hazard free delay fault testable" is presented. In contrast to existing results that consider either "single path propagating hazard free robust tests" or "general robust tests" we consider "multiple path propagating hazard free robust tests" in our analysis.

In the absence of information about the layout, test generation and fault simulation systems must target all bridging faults. A novel algorithm, that is both time and space efficient, for simulating I/sub DDQ/ tests for all two-line bridging faults in combinational circuits is presented. Simulation results using randomly generated test sets point to the computational feasibility of targeting all two-line bridging faults. On a more theoretical note, we show that the problem of computing I/sub DDQ/ tests for all two-line bridging faults, even in some restricted classes of circuits, is intractable, and, even under some pessimistic assumptions, a complete I/sub DDQ/ test set for all two-line bridging faults also covers all multiple line, single cluster bridging faults.

This paper describes a diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and space efficient. The simulator represents indistinguishable classes of faults as memory efficient lists. The use of lists reduces the number of output response comparisons between faults and hence speeds up the simulation process. The lists also make it easy to drop faults when they are fully distinguished from other faults. Experimental results on the ISCAS89 circuits show that the simulator runs significantly faster than an earlier work based on distinguishability matrices and is faster and more memory efficient than a recent method based on lists of indistinguishable faults. The paper provides the first reports on pessimistic and optimistic diagnostic measures for all faults of the large ISCAS circuits. 1 Introduction The aim of fault location or diagnosis is to locate device failures. Diagnosis may be intended for identification and replacement of a faulty sub-circui...

Adaptive diagnosis, a paradigm for diagnosis, is defined. A system based on this paradigm, for I/sub DDQ/ measurement based diagnosis of bridging faults, is reported. Experimental evaluation of the system shows it to be substantially superior to existing systems, especially for larger circuits.

To ensure the production of reliable circuits and fully testable unpackaged dies for MCMs burn-in, both dynamic and monitored, remains a feasible option. During this burn-in process the circuit needs to be stressed for an extended period of time. This requires computation of cyclic input sequences to stress the circuit. A taxonomy of stress related problems for full scan circuits is presented. It is shown that there are efficient ways to compute the sequences for many variations of monitored burn-in problems. Preliminary experimental results on ISCAS89 benchmark circuits are presented.

Selecting a small subset of the set of functional vectors for performing I/sub DDQ/ measurement has previously been studied for leakage but not for bridging faults. Algorithms for this problem for all two line bridging faults, in combinational and sequential circuits, along with experimental results are presented.

Two faults are said to be equivalent, w.r.t. a test set T, iff they cannot be distinguished by any test in T. The sizes of the equivalence classes are used as a basis for comparing the diagnostic capability of two given test sets. The authors show that modifications of single stuck-at fault simulators leads to very efficient diagnostic simulators when compared with those reported in the literature.>

Article An algorithm for diagnosing two-line bridging faults in combinational circuits Share on Authors: Sreejit Chakravarty View Profile , Yiming Gong View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 520–524https://doi.org/10.1145/157485.165012Online:01 July 1993Publication History 48citation177DownloadsMetricsTotal Citations48Total Downloads177Last 12 Months2Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

In the absence of information about the layout and for better defect coverage test generation and fault simulation systems must target all bridging faults. The authors show that an I/sub DDQ/ Test Set that detects all two line bridging faults also detects all multiple line, single cluster bridging faults. A novel algorithm for simulating I/sub DDQ/ tests for all two-line bridging faults in combinational circuits is presented. Experimental results on using randomly generated I/sub DDQ/ test sets for detecting bridging faults are presented. These results point to the computational feasibility of targeting all two line bridging faults in combinational circuits, for the purpose of I/sub DDQ/ test generation.>

Binary decision diagrams (BDDs) are a representation of Boolean functions. Its use in the synthesis, simulation, and testing of Boolean circuits has been proposed by various researchers. In all these applications of BDDs solutions to some fundamental computational problems are needed. A characterization of BDDs in terms of the complexity of these computational problems is presented. A tighter bound on the size of an ordered BDD that can be computed from a given Boolean circuit is presented. On the basis of the results, a case is made for exploring the use of repeated BDDs, with a small number of repeated variables, and free BDDs for some applications for which only ordered BDDs have been used so far.>

Functional cells are a physical realization of complex MOS gates. Efficient algorithms for minimizing the width of a functional cell are known. Every solution to the width minimization problem leads to a cell of a certain height. It is shown that, even for functional cells of complex MOS gates represented by series-parallel transistor networks, the problem of finding a solution of minimum width that also minimizes the height is NP-hard.>

We show that a class of CMOS circuits is a testable realization and static CMOS circuits synthesized by some existing synthesis systems belongs to this class. We propose a more “direct” solution to the problem of computing robust test-pairs for stuck-open faults by defining a new six-valued logic. This in turn gives us a solution to the problem of identifying stuck-open testable circuits.

Algorithms for the following two problems are presented: (1) computing detection probability of stuck-at faults (CDP), and (2) computing signal probability (CSP). These problems arise in the context of random testing, pseudorandom testing, and testability analysis of combinational circuits. The algorithm for CDP combines the notion of supergates and a refinement of th algorithm for CDP presented in the work of S. Chakravarty and H.B. Hunt, III (1986). The algorithm for CDP can be used to compute the exact value of detection probability of multiple stuck-at faults in circuits with multiple outputs. Single-input, single-output pseudo gates are inserted to model stuck-at faults and derive an equivalent single-output circuit. CDP is thus reduced to the problem of computing the probability distribution of the output over the set of four logic values (0, 1d, d). The algorithm for CDP uses an efficient enumeration algorithm. The authors show how the enumeration algorithm can be used to refine the algorithm for CSP.>

A sequence of input vectors which detects all transistor stuck-open faults in a CMOS combinational circuit is a complete test sequence. Given a complete set of two-pattern tests for transistor stuck-open faults in a CMOS circuit, it is shown that a complete test sequence of minimum length can be obtained efficiently. A precise description of this problem and examples to illustrate the method are presented.>

The KR realization (see S. Kundu and S.M. Reddy, Proc. 18th Int. Fault-Tolerant Computing Symp., p.220-25 1988) was proposed with the aim of designing testable CMOS combinational circuits using only primitive gates and no extraneous hardware. It is shown that for some useful Boolean functions the size of the KR realization is exponential in the number of input variables. The author presents a testable realization of a CMOS combinational circuit, with respect to FET (field-effect-transistor) stuck-open faults, named FM-CMOS. It uses only two-input multiplexers and, to an extent, addresses the size-problem of the KR realization. More specifically, it is shown that for some useful Boolean functions for which the size of the KR realization is exponential in the number of input variables the size of the FM-CMOS realization is polynomial in the number of input variables. For this reason, it is proposed that the FM-CMOS realization be used in conjunction with the KR realization. The results are applied to design a testable n-b CMOS adder that uses only O(n) FETs.>

The problem of detecting sneak paths in transistor networks arises in the minimization of transistor networks. It is shown that the problem of detecting consistent sneak paths in very simple transistor networks is co-NP-complete.>

The authors show that the problem of obtaining a minimum complete test set is NP-complete for monotone PLAs even when each product term of the PLA contains at most two literals. Using the ideas developed in the proof of this result, they resolve an open question due to B. Krishnamurthy and S.B. Akers (1984). The authors also show that given a complete test set T, the problem of obtaining a minimum test set contained in T is NP-complete even for two-level monotone circuits.>

The following problems pertinent to testing CMOS gates are considered. CTSOF: the problem of computing a two-pattern test sequence that detects the fault 'T Stuck-Open' given a CMOS gate G and an FET T in G. CTSAF: the problem of computing an input vector that detects the fault in which the output of G is stuck at a given a CMOS gate G and a constant a epsilon (0, 1). It is shown that bounded degree fanout (bounded by 2) in unate CMOS gates is enough to make CTSOF CoNP-hard, CTSOF is harder than CTSAF, and an upper bound on the complexity of both CTSOF and CTSAF is O(2/sup f/*m), where f is the number of fanout variables and m is the number of FETs in the CMOS gate. It is also shown that there exists a CMOS gate realization of Boolean functions named BC-CMOS circuits such that for every Boolean function there exists a BC-CMOS circuit, there exists a linear time algorithm for both CTSOF and CTSAF for BC-CMOS circuits, and CMOS gates derived from Boolean expressions using Shannon's expansion are BC-CMOS circuits.>