Although deemed as one of the promising candidates to substitute CMOS transistors in the sub-10 nm regime, fabrication of Carbon Nanotube Field-Effect Transistors (CNFET) is still experiencing significant process variations. In this paper, we consider carbon nanotube diameter process variation in CNFET analog circuit sizing design. We systematically study a robust sizing methodology for designing analog CNFET circuits. We propose a multi-objective deterministic sizing flow to approach the best performance of analog CNFET circuits even under device parameter process variation. We use a design centering approach to obtain the optimal value of design parameters to ensure a robust circuit. Moreover, we have developed a generic multi-objective deterministic sizing optimization methodology using SPICE simulation for circuit performance verification by combining generalized boundary curves and normal boundary intersection schemes. The experimental results demonstrate that our proposed method can better approach the Pareto front than another common stochastic multi-objective optimizer.

In this paper, we examine a method of constructing a self-synchronizing stream cipher referred to as statistical cipher feedback (SCFB). Although recently studied as a mode for block ciphers, we explicitly consider the application of SCFB to hardware-oriented stream ciphers. Specifically, we show that SCFB can be used to realize a self-synchronizing stream cipher that has the characteristics of compact, efficient hardware implementations and is secure given that the underlying synchrononous stream cipher is secure. Further, we consider the communication properties of the SCFB system and examine the relationships between these properties and the implementation characteristics.

In this paper, we investigate the burst error properties of the block cipher mode of operation referred to as statistical cipher feedback mode SCFB. SCFB was introduced as an efficient method of providing physical layer security by configuring a block cipher to operate as a self-synchronizing stream cipher. The self-synchronization property of a stream cipher allows the system to recover from data losses that might occur in the communication channel. The research presented in this paper investigates the properties of the post-decryption output of the cipher in response to bit errors in the communication channel. In particular, the probability distribution of the length of error bursts is investigated through simulation, and a theoretical analysis is given for an upper bound on the probability of a burst longer than a given length. The results can be used to determine appropriate selections for parameters of the cipher mode and the specifications of the communication system, such as the error correction scheme and packet size. Copyright © 2016 John Wiley & Sons, Ltd.

Although power analysis attacks have been extensively applied to block ciphers, only limited research has been done to analyze their effectiveness on stream cipher hardware implementations. In this paper, we investigate methods of simple power analysis applied to stream ciphers based on multiple feedback shift registers (FSRs) and demonstrate the effectiveness of the methods by examining the cipher Grain which involves both a linear and a nonlinear FSR. A divide-and-conquer attack is presented where the attacker guesses the bit values of the FSRs independently and then checks the correctness of the guess using information derived from measured power consumption of the cipher core. Experimental results of the attack applied to simulated power data obtained for a CMOS implementation of Grain show that it is possible to recover directly the cipher state using only about 3000 power samples. For ciphers constructed using a general architecture of multiple FSRs, the attack has the potential to be successful with a complexity substantially less than exhaustive key search.

Linear feedback shift registers (LFSRs) and nonlinear feedback shift register (NLFSRs) are major components of stream ciphers. It has been shown that, under certain idealised assumptions, LFSRs and LFSR‐based stream ciphers are susceptible to cryptanalysis using simple power analysis (SPA). In this study, the authors show that SPA can be practically applied to a CMOS digital hardware circuit to determine the bit values of an NLFSR and SPA therefore has applicability to NLFSR‐based stream ciphers. A new approach is used with the cryptanalyst collecting power consumption information from the system on both edges (triggering and non‐triggering) of the clock in the digital hardware circuit. The method is applied using simulated power measurements from an 80‐bit NLFSR targeted to an 180 nm CMOS implementation. To overcome inaccuracies associated with mapping power measurements to the cipher data, the authors offer novel analytical techniques which help the analysis to find the bit values of the NLFSR. Using the obtained results, the authors analyse the complexity of the analysis on the NLFSR and show that SPA is able to successfully determine the NLFSR bits with modest computational complexity and a small number of power measurement samples.

Parasitic capacitance of interconnects in the analog and mixed-signal VLSI circuits can be modeled by using physics equations or empirical curve fitting. In this paper, we propose an analytical model for computing parasitic capacitance between interconnects on different layers or on the same layer. In our method, electric flux is approximated to model different capacitive components, which combine to determine the overall equivalent capacitance. We first derive a general template for the fringe capacitance based on fundamental electromagnetic principles, followed by a fitting technique in order to reach outstanding accuracy. Based on our approach that includes no complex operators, capacitance of typical interconnect geometries can be efficiently computed. The proposed model is verified in comparison with the extracted results derived from commercial tools. The experimental results show that our proposed method can best approach the extracted results yet with significantly reduced computation time.

ABSTRACT In this paper, we focus on the energy efficiency of secure communication in wireless sensor networks (WSNs). Our research considers link layer security of WSNs, investigating both the ciphers and the cryptographic implementation schemes, including aspects such as the cipher mode of operation and the establishment of initialization vectors (IVs). We evaluate the computational energy efficiency of different symmetric key ciphers considering both the algorithm characteristics and the effect of channel quality on cipher synchronization. Results show that the computational energy cost of block ciphers is less than that of stream ciphers when data are encrypted and transmitted through a noisy channel. We further investigate different factors affecting the communication energy cost of link layer cryptographic schemes, such as the size of payload, the mode of operation applied to a cipher, the distribution of the IV, and the quality of the communication channel. A comprehensive performance comparison of different cryptographic schemes is undertaken by developing an energy analysis model of secure data transmission at the link layer. This model is constructed considering various factors affecting both the computational cost and communication cost, and its appropriateness is verified by simulation results. In conclusion, we recommend using a block cipher instead of a stream cipher to encrypt data for WSN applications and using a cipher feedback scheme for the cipher operation, thereby achieving energy efficiency without compromising the security in WSNs. Copyright © 2011 John Wiley & Sons, Ltd.

In this paper, we introduce a new block cipher mode of operation targeted to providing high-speed hardware-based self-synchronizing stream encryption. The proposed mode is a modification of statistical cipher feedback (SCFB) mode and is designed to be implemented using pipeline architectures for the block cipher. We refer to the mode as pipelined SCFB mode or PSCFB. In this paper, we consider the implementation characteristics and show that PSCFB is able to achieve speeds that are very close to pipelined block cipher implementations configured for counter mode. Such speeds are achieved with modest latency through the system and a small amount of memory required for the system queues with a provable guarantee of no queue overflow. Further, we examine the characteristics of PSCFB mode in response to bit errors and synchronization losses in the communication channel. Specifically, we show that the error propagation factor is modest and comparable to conventional SCFB and that synchronization recovery delay is reasonable given the expectation that synchronization loss is infrequent. Given the high efficiency and good communication characteristics of the mode, it is concluded that PSCFB is an excellent choice for high-speed network applications requiring stream-oriented encryption with self-synchronizing capabilities.

In this paper, we focus on secure communication in wireless sensor networks (WSNs). Specifically, we investigate different factors which affect the energy cost of link layer cryptographic security schemes, such as the payload size, the source of the initialization vector, and the channel quality. We propose an approach to evaluate the performance of cryptographic communication schemes by developing an analysis model considering these factors. The appropriateness of this model is supported by simulation results. In conclusion, we recommend cipher feedback (CFB) mode for the cipher operation, thereby achieving energy efficiency without compromising the security.

In this paper, we examine the digital hardware design and implementation of a novel compact block cipher, referred to as PUFFIN, that is suitable for embedded applications. An implementation of PUFFIN targeted to ASIC technology is considered. The proposed block cipher is designed to have a 64-bit block size, a 128-bit key, and is capable of both encryption and decryption operations. The cipher structure is based on the following features: a simple encryption process composed of permutations and substitutions based on 4 times 4 S-boxes, an identical datapath for both encryption and decryption facilitated by involutional operations, and a straightforward on-the-fly subkey generation composed of only a permutation and bit inversions. PUFFIN is found to perform well for implementations based on 0.18-micron CMOS technology. In comparison to other lightweight ciphers, PUFFIN has preferred features, low hardware complexity, and good throughput.

ICEBERG is a block cipher that has been recently proposed for security applications requiring efficient FPGA implementations. In this paper, we investigate a compact ASIC implementation of ICEBERG and consider the novel application of concurrent error detection to protect the implementation from fault-based attacks. The compact architecture of ICEBERG requires about 5800 gates with a throughput of 552 Mbps in an ASIC implementation based on 0.18 μm CMOS technology. The addition of an effective multiple parity concurrent error detection scheme to protect the hardware from fault attacks results in a 62% area overhead.

Abstract — This paper presents the architecture design as well as the performance analysis of a new cell-based multicast switch for broadband communications. Using distributed control and a modular design, the Balanced Gamma (BG) switch features a high performance for unicast, multicast and combined traffic under both random and bursty conditions. Although it has buffers on input and output ports, the multicast BG switch follows predominantly an output-buffered architecture. The performance is studied under uniform and non-uniform multicast traffic in terms of cell loss ratio and cell delay. The results are compared with those from an ideal pure output-buffered multicast switch to demonstrate how close its performance is to that of the ideal but impractical switch. Comparisons with other published switches reveals the superior of the BG switch and the tradeoffs between complexity and performance in a packet switch design. It is shown that the multicast BG switch achieves a performance close to the ideal switch while keeping hardware complexity reasonable. Index Terms — Multicast, Balanced Gamma (BG) switch, performance analysis, multistage interconnection network (MIN),

This paper presents an analytical model for the performance analysis of a new cell-based multicast switch for broadband communications. Using distributed control and a modular design, the Balanced Gamma switch features a high performance for unicast, multicast and combined traffic under both random and bursty conditions. Although it has buffers on input and output ports, the multicast BG switch follows predominantly an output-buffered architecture. The analytical model follows the three phase switching operation. The performance is evaluated under multicast random traffic in terms of cell loss ratio and cell delay. Performance under bursty traffic is studied through simulation and the results are compared to those of an ideal pure output-buffered multicast switch.

In this paper, we examine a recently proposed mode of operation for block ciphers which we refer to as statistical cipher feedback (SCFB) mode. SCFB mode configures the block cipher as a keystream generator for use in a stream cipher such that it has the property of statistical self -synchronization, thereby allowing the stream cipher to recover from bit slips in the communication channel. Statistical self-synchronization involves feeding back ciphertext to the input of the block cipher similar to the conventional cipher feedback (CFB) mode, except that the feedback only occurs when a special synchronization pattern is recognized in the ciphertext. In the paper, we examine the efficiency, resynchronization, and error propagation characteristics of SCFB and compare these to conventional modes such as CFB and output feedback (OFB). In particular, we study these characteristics of SCFB as a function of the synchronization pattern size. As well, we examine implementation issues of SCFB, focusing on the buffer requirements and resulting delay for a practical realization of the cipher. We conclude that SCFB mode can be used to provide practical, efficient, self-synchronizing implementations for stream ciphers. In particular, SCFB mode is best used in circumstances where slips are a concern and where implementation efficiency is a high priority in comparison to encryption latency.

The paper presents the design and implementation of a new multicast switch for broadband communications. Using distributed control and modular design, the multicast balanced gamma (BG) switch features a scalable, high performance architecture for unicast, multicast and combined traffic under both uniform and non-uniform traffic conditions. The important design characteristic of the switch is that a distributed cell replication function for multicast cells is integrated into the functionality of the switching element (SE) with the self-routing and conflict contention functions. We discuss in detail the design issues associated with the multicast functionality of the switch. VLSI implementation results for the BG switch fabric using 0.18 /spl mu/m CMOS technology are presented. Scalability and performance properties of the multicast BG switch are also briefly discussed.

In this paper, we examine a recently proposed mode of operation for block ciphers which we refer to as statistical cipher feedback (SCFB) mode. SCFB mode configures the block cipher as a keystream generator for use in a stream cipher such that it has the property of statistical self-synchronization, thereby allowing the stream cipher to recover from slips in the communications channel. Statistical self-synchronization involves feeding back ciphertext to the input of the keystream generator similar to the conventional cipher feedback (CFB) mode of block ciphers, except that the feedback only occurs when a special pattern is recognized in the ciphertext. In the paper, we examine the efficiency, resynchronization, and error propagation characteristics of SCFB and compare these to the conventional modes of CFB, output feedback (OFB), and counter mode. In particular, we study these characteristics of SCFB as a function of the synchronization pattern size. We conclude that, although it can take significantly longer to resynchronize, SCFB mode can be used to provide self-synchronizing implementations for stream ciphers that are much more efficient than conventional CFB mode and that have error propagation characteristics similar to CFB mode.

We examine the information leakage between sets of plaintext and ciphertext bits in symmetric-key block ciphers. The paper demonstrates the effectiveness of information leakage as a measure of cipher security by relating information leakage to linear cryptanalysis and by determining a lower bound on the amount of data required in an attack from an upper bound on information leakage. As well, a model is developed which is used to estimate the upper bound on the information leakage of a general Feistel (1975) block cipher. For a cipher that fits the model well, the results of the analysis can be used as a measure in determining the number of rounds required for security against attacks based on information leakage. It is conjectured that the CAST-128 cipher fits the model well and using the model it is predicted that information leaked from 20 or fewer plaintext bits is small enough to make an attack on CAST-128 infeasible.

This paper develops analytical models for the avalanche characteristics of a class of block ciphers usually referred to as substitution-permutation encryption networks or SPNs. An SPN is considered to display good avalanche characteristics if a one bit change in the plaintext input is expected to result in close to half the ciphertext output bits changing. Good avalanche characteristics are important to ensure that a cipher is not susceptible to statistical attacks and the strength of an SPN's avalanche characteristics may be considered as a measure of the randomness of the ciphertext. The results presented in this paper demonstrate that the avalanche behavior of encryption networks can be improved by using larger S-boxes. As well, it is shown that increasing the diffusion properties of the S-boxes or replacing the permutations by diffusive linear transformations is effective in improving the network avalanche characteristics.>

In this paper we examine a class of product ciphers referred to as substitution-permutation networks. We investigate the resistance of these cryptographic networks to two important attacks: differential cryptanalysis and linear cryptanalysis. In particular, we develop upper bounds on the differential characteristic probability and on the probability of a linear approximation as a function of the number of rounds of substitutions. Further, it is shown that using large S-boxes with good diffusion characteristics and replacing the permutation between rounds by an appropriate linear transformation is effective in improving the cipher security in relation to these two attacks.