This paper proposes a new framework for inserting test points at RTL (Register Transfer Level) enabling better Power-Performance-Area-Testability (PPAT) optimization during synthesis and yielding quick turn-around time and faster Time-to-Market (TTM). It introduces the concept of editable nodes in RTL designs and avoids locations that are difficult to modify. Early identification of editable nodes in the RTL to guide and drive the test point analysis engine helps in improving the quality of test points inserted into the design. In addition, the proposed methodology involves optimization of the RTL, a quick synthesis of the design, and test point analysis at the netlist-level by avoiding locations that are pre-marked as ‘don't-touch’. Once the test point locations are identified in an internal unmapped gate representation, they are back annotated and inserted in the RTL. Some locations can be directly mapped back, whereas some other locations can be mapped back to expression and sub-expression boundaries in RTL with the help of additional information that is exported during the logic synthesis step. Experimental results on several industrial designs show that the effectiveness of test points inserted at RTL closely matches their counterparts at the gate-level with added benefits of better area, timing, test coverage, and pattern count optimization early in the design flow.

Under the functional safety standard ISO26262, automotive systems require testing in the field, such as the power-on self-test (POST) . Unlike the production test, the POST requires reducing the test application time to meet the indispensable test quality (e.g., >90% of latent fault metric) of ISO26262. This article proposes a test point insertion technique for multi-cycle power-on self-test to reduce the test application time under the indispensable test quality. The main difference to the existing test point insertion techniques is to solve the fault masking problem and the fault detection degradation problem under the multi-cycle test. We also present the method to identify a user-specified amount of test points that could achieve the most scan-in pattern reduction for attaining a target test coverage. The experimental results on ISCAS89 and ITC99 benchmarks show 24.4X pattern reduction on average to achieve 90% stuck-at fault coverage confirming the effectiveness of the proposed method.

In recent years, low power devices have become widely designed. Since the power supply design is based on the user operation, there is the possibility that it can malfunction in conventional scan testing on account of the excessive power consumption during scan testing. In order to overcome this problem, we have combined and adopted various scan testing techniques. This paper presents a scan testing approach that is demonstrated to be effective for ultra-low power devices. It splits one scan shift clock into several scan shift clocks per clock domain. Moreover, it changes the scan shift clock speed to cope with the inrush current. These clock controls are made possible by our own test clock controller.

Multi-cycle Test applies more than one capture cycles during the capture operation which is a promising way to reduce the test volume of Logic-BIST (Logic Built-in Self-Test) based POST (Power-on Self-Test) for achieving high fault coverage. However, the randomness loss of the capture patterns due to the large number of capture cycles obstructs the further improvement of fault coverage and pattern reduction. In this paper, we propose a novel approach to control the capture patterns by modifying the captured values of scan Flip-Flops (FFs) during capture operation to enhance the test quality of the capture patterns. In the approach, we insert FF-Control circuits between the scan FFs and the combinational circuit to improve the randomness of the capture patterns by loading toggle vectors/pseudo-random vectors. The experimental results of ISCAS89 and ITC99 benchmarks validated the effectiveness of the proposed methods in fault coverage improvement and random pattern reduction for Logic-BIST.

To attain the requirement of ISO26262 standard, the POST for automotive MCU needs to achieve high Latent Fault (LF) metric (>90% for ASIL D) within limited test application time (TAT). In this paper, we propose a new DFT technique named Fault-Detection-Strengthened (FDS) method to enhance the effect of test pattern reduction of the multi-cycle test for shortening the TAT of POST, and develop an original in-house tool named FVP-TPI (Fault Vanishing Point-TPI) to implement the FDS method to automotive MCU. The evaluation results on a latest commercial automotive MCU (62M gates) confirm the effectiveness (test volume compaction) and the practicability (smaller hardware overhead, shorter period of DFT) of the method.

The IP session highlights three innovative practices in Asia, which include low cost testing of analog front-end circuits, evaluation of complex analog filter and power reduction of power-on self-test for automotive MCU.

ISO 26262 sets requirements for automotive safety systems to decrease hazards caused by LSI logic failures. Several approaches are possible to determine that a logical fault exists and for the system to respond before it becomes a system failure. However, these approaches are often expensive in terms of logic and design overhead. They can take many cycles before a high percentage of potential fault sites are checked. This paper presents a deterministic ATPG-based approach to detect faults during runtime operation. The benefit is lower area and less design impact compared to logic BIST while providing high coverage quickly and low power operation. We describe the implementation of deterministic ATPG-based runtime test (DART) based on embedded compression technology implemented in ICs for the R-Car autonomous vehicle platform.

Today, at-speed test cost comprises a majority of the total test cost of a design. This derives from the fact that if the design has numerous data transfers between clock domains, we must generate test patterns for all of the synchronous data transfers to guarantee high reliability. Conventionally, at-speed test patterns are generated for each of the transfers separately. In order to reduce at-speed test application time, we take an approach to increase the number of the transfers tested concurrently. Evaluation results show that our approach is effective for that purpose.

This paper reviews the major trends in the next generations of optical access systems. The motivations behind the development of advanced systems are presented, and then three major technical areas are explored. First, the field of 10 Gbit/s passive optical network (PON) systems is laid out. Second, the various solutions to long reach PON are reviewed. Third, the very wide and exciting field ofWDMand hybrid WDM-TDMA PONs are discussed. The paper closes with a review of the expected timeline for the standardization of these technologies.

Low power design is becoming the mainstream in VLSI. However, since most of the technologies minimizing power consumption have only focused on normal mode operation, test mode operation is often posing the high power consumption because of the high switching activity during scan shift operation. On the other hand, test data volume has become big issue as the size of digital designs continues to grow. Logic built-in self-test (LBIST) is well known as one of the technologies to reduce test data volume. In general, LBIST uses pseudorandom pattern generator (PRPG) with high switching activity. Therefore LBIST makes high power consumption during scan shift operation. As the results, it increases test time (costs) because test engineer has to slow down shift speed to solve power issue. Now, we propose new technique called CooLBIST that controls switching activity during scan shift operation of LBIST. Application result shows that new activity control technique succeeds in reducing the switching activity during scan shift operation without a decline in fault coverage.