This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as compared to conventional SerDes Designs, making it very attractive for modest budget multi-core and multi-processor ASICs with wide communication buses that are difficult to accommodate within the pin count of commonly available packaging. The design employs a “Statistical Random Sampling Technique ” to observe and adjust the synchronization and serialization signals at start up rather than using a resource-heavy PLL or DLL based frequency multiplier/synthesizer and clock data recovery circuits. The serialization and deserialization logic is based on standard cell technology that makes the design highly portable. Multiple serial lines are bundled with a strobe that is used as a reference signal for deserialization. Data-to-strobe timing skew is compensated by adjusting the launch times of strobe and data symbols at the sender side. The edges of the strobe are set within the eye of data symbols to have maximum timing margin, which makes the design inherently tolerant of jitter. Power consumption of the proposed SerDes design is 30 mW per serial link targeted to IBM Cu-11(130 nm) Technology, nearly a 2.5x improvement over the conventional design with a 60 % less area requirement.

This paper introduces a technique to measure and adjust the relative phase of on-chip high speed digital signals using a random sampling technique of inferential statistics. The proposed technique as applied to timing uncertainty mitigation in the signaling of a digital system is presented as an example; the relative phase information is used to minimize the timing skew. The proposed circuit captures the state of the signals under measurement simultaneously at random instants of time and gathers a large sample data to estimate the relative phase between the signals. By carefully premeditating the sample size, the accuracy and confidence of the result can be set to a level as high as desired. Accurately sensed value of relative phase enables the correction circuit to reduce the maximum correction error, less than half the maximum delay resolution unit available for adjustment. A pure standard cell based circuit design approach is used that reduces the overall design time and circuit complexity. The test results of the proposed circuit manifest a very close correlation to the simulated and theoretically expected results. The random sampling unit (RSU) circuit proposed for phase measurement in this paper occupies 3350 (mum)2area in 130nm technology, which is an order of magnitude smaller than what is required for its analog equivalent in the same technology

Cyclops is a new architecture for high-performance parallel computers that is being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip SMP (symmetric multiprocessor) system with multiple threads of execution, embedded memory and integrated communications hardware. Massive intra-chip parallelism is used to tolerate memory and functional unit latencies. Large systems with thousands of chips can be built by replicating this basic cell in a regular pattern. In this paper, we describe the Cyclops architecture and evaluate two of its new hardware features: a memory hierarchy with a flexible cache organization and fast barrier hardware. Our experiments with the STREAM benchmark show that a particular design can achieve a sustainable memory bandwidth of 40 GB/s, equal to the peak hardware bandwidth and similar to the performance of a 128-processor SGI Origin 3800. For small vectors, we have observed in-cache bandwidth above 80 GB/s. We also show that the fast barrier hardware can improve the performance of the Splash-2 FFT kernel by up to 10%. Our results demonstrate that the Cyclops approach of integrating a large number of simple processing elements and multiple memory banks in the same chip is an effective alternative for designing high-performance systems.

The IBM Blue Gene project has endeavored into the development of a cellular architecture computer with millions of concurrent threads of execution. One of the major challenges of this project is demonstrating that applications can successfully exploit this massive amount of parallelism. Starting from the sequential version of a well known molecular dynamics code, we developed a new application that exploits the multiple levels of parallelism in the Blue Gene cellular architecture. We perform both analytical and simulation studies of the behavior of this application when executed on a very large number of threads. As a result, we demonstrate that this class of applications can execute efficiently on a large cellular machine.

article Free Access Share on The GF11 supercomputer Authors: John Beetem IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NYView Profile , Monty Denneau IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NYView Profile , Don Weingarten IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NYView Profile Authors Info & Claims ACM SIGARCH Computer Architecture NewsVolume 13Issue 3June 1985 pp 108–115https://doi.org/10.1145/327070.327139Published:01 June 1985Publication History 94citation465DownloadsMetricsTotal Citations94Total Downloads465Last 12 Months53Last 6 weeks14 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF