Trimming is a critical step in ensuring the performance uniformity of integrated circuits (ICs), typically achieved by adjusting control variables to align target specifications. However, in practical scenarios, the relationship between control variables and performance metrics often exhibits nonlinearity, posing challenges for traditional trimming methods in balancing accuracy and efficiency. To address this issue, this paper proposes a fast nonlinear trimming method driven by performance deviation. The proposed approach learns the mapping between performance deviation and control variables, enabling efficient inverse inference without relying on exhaustive search or iterative back-substitution. Experimental results demonstrate that our method reduces the average number of iterations by 43.3% and achieves a 77.6% success rate in meeting target specifications on the first attempt. These findings highlight the method’s advantages in accuracy, efficiency, and feasibility under complex nonlinear trimming scenarios, as well as its potential for generalization and practical deployment.

A die-level design-for-test architecture for 3D stacked ICs is proposed. The main component of this architecture is a newly proposed configurable boundary cell, based on which flexible parallel test is achieved. Both of the number of parallel scan chains and their lengths can be configured during test. This test architecture features light-weight, high flexibility in parallel test configuration , modularity, and IEEE P1149.1 compatibility. In this work, both infrastructure and implementation aspects are illustrated. Experimental results demonstrate desired test acceleration. The acceleration ratio approximately reaches its limit, which equals the number of parallel scan chains, when the number of test vectors is over 300.

Light field (LF) imaging enables new possibilities for digital imaging, such as digital refocusing, changing of focus plane, changing of viewpoint, scene-depth estimation, and 3D scene reconstruction, by capturing both spatial and angular information of light rays. However, one main problem in dealing with LF data is its sheer volume. In this context, efficient compression methods are needed for such a particular type of content. In this paper, we propose a content-based LF image-compression method with Gaussian process regression to improve the compression efficiency and accelerate the prediction procedure. First, the LF image is fed to the intra-frame codec of HEVC. In the prediction procedure, the prediction units (PUs) are classified as non-homogenous texture units, homogenous texture units, and visually flat units, based on the content property of the LF image. For each category, we design a corresponding Gaussian process regression (GPR)-based prediction method. Moreover, we propose a classification mechanism to exactly decide to which category the current PU belongs, so as to adjust the trade-off between the computational burden and the LF image coding efficiency. Experimental results demonstrate that the proposed LF image compression method is superior to several other state-of-the-art compression methods in terms of different quality metrics. Furthermore, the proposed method can also achieve a good visual quality of views rendered from decoded LF contents.

A precomputed core test set contains a large number of don't cares (x's) that can be effectively exploited to improve test data compression (TDC). Extending pattern run-length coding, we present a novel strategy that propagates thex's of a reference pattern to a new reference pattern in such a way that the reference pattern is xor-ed with the pattern to be encoded. Thex-propagating strategy can increase the probability of a reference pattern being coding-compatible with the pattern to be encoded, and its validity can be established by filling somex's of the already encoded patterns in backtracing way. How our strategy is used for TDC is demonstrated. Experimental results for large ISCAS89 benchmarks show that, compared to the recently proposed schemes, our technique can effectively improve compression and simplify on-chip decoder, and work better when used for core-unified TDC.

A new scheme of test data compression, namely equal-run-length coding (ERLC) scheme is presented, which is based on run-length. It first considers both types of runs of 0's and 1's, then it further explores the relationship between two consecutive runs on the basis of the traditional characteristic of run coding which uses shorter codeword to represent longer symbol (run-length). This scheme uses two shorter codewords to represent the whole second run of two consecutive runs, the lengths of which are the same. Compared with other already known schemes this scheme has some characteristics, such as high compression ratio, easy control and implementation. The performance of the algorithm is mathematically analyzed and its merits are experimentally confirmed on the larger examples of the ISCAS89 benchmark circuits.

A new test vector compression/decompression scheme, namely a scheme of logic operation between adjacent bits (LOBAB) is presented, which is based on bitwise logic operation between itself and its previous bit. It turns all kinds of series including continuous series, such as a series of all 0s and all 1s, and reversal series, such as a series of 01 and 10, into series of all 0s by logic operation between adjacent bits. On one hand, the two kinds of series, continuous series and reversal series, are both taken into account, which decreases the number of division to the original test data. On the other hand, all series are turned into series of all 0s, which eases the process of encoding and decoding. Compared with other already known schemes this scheme has some characteristics, such as high compression ratio, easy control and implementation. The performance of the algorithm is mathematically analyzed and its merits are experimentally confirmed on the larger examples of the ISCAS89 benchmark circuits.

A new test data compression scheme is introduced in this paper. The proposed scheme encodes the test data provided by the core vendor, using a new and very effective compression scheme based on OLEL coding. In this scheme, codeword is divided into two parts according to the position: odd bits and even bits. The odd bits of codeword are used to represent the length of runs and the even bits of codeword are used to represent whether a run is finished. The length of codeword is in accordance with the distribution of the length of run in actual test data, and thus, significant compression improvements compared with the already known schemes are achieved. A simple architecture is proposed for decoding the compressed data on chip. Its hardware overhead is very low and comparable to that of the most efficient methods in the literature. Experimental results for the six largest ISCAS-89 benchmark circuits show that the proposed scheme is obviously better than the already known schemes in the aspects of compression ratio and the decompression structure, such as Golomb, FDR, and MTC coding schemes.

A novel test data compression coding scheme, block marking and updating coding, is proposed in this paper. Test data in the test set was divided into successive fixed-length vectors, called blocks, and then they were marked according to their compatibility compared with a reference vector. An operation that is similar to difference and a technique that strategically fills in don 't-care bits are combined to increase the probabilities of compatibility or inverse compatibility. It effectively compresses test data and its decompression structure is very simple. Experimental results of ISCAS-89 benchmark circuits show that the scheme is very effective.

A novel collaborative scheme of test data compression based on fixed-plus-variable-length (FPVL) coding is presented, with which the test data can be compressed efficiently. In this scheme, code words are divided into fixed-length head and variable-length tail. In order to obtain further compression, the highest bit of the tail is reduced from the code words, because all of the highest bits in the tail section of the tail are the same as 1. A special shift counter is also used, which further eases the control circuit. Experimental results of the Mintest fault sets of part ofISCAS-89 benchmark circuits show that the proposed scheme is obviously better than traditional coding methods in the compression ratio and the implementation of decompression, such as Golomb, FDR, VIHC, v9C coding.

Web-based instruction is a new learning medium that offers many advantages in educational settings. The main advantage is reflected in its non-linear interaction. Students can control the pace and sequence of instruction and make personally meaningful choices which in theory should assist in developing their cognitive structure. However, in practice some learners may have difficulties in making the learning paths by themselves. Some influencing factors of learning interaction in Web-based instruction are discussed according to individual differences. Data were collected from some classes in Anqing Normal College of Anhui province. A total 350 available responses were analyzed. We identified three results from this study: (1) learners show positive attitudes towards L-L Web-based interaction learning. And the form of network application which they like best and use most frequently is finishing homework through group cooperation. (2) During the process of finishing homework, learners actively seek for and sort out materials, to which comparatively deep analysis is made. And L-I Web-based interaction learning is also comparatively active. (3) The spontaneous learning ability and knowledge techniques of the learners have striking predication to successful Web-based learning, and the predication effect of the visual style, hearing style and acting style are not striking