Transactional memory is a promising mechanism for synchronizing concurrent programs that eliminates locks at the expense of hardware complexity. Transactional memory is a hard feature to verify. First, transactions comprise several instructions that must be observed as a single global atomic operation. In addition, there are many reasons a transaction can fail. This results in a high level of non-determinism which must be tamed by the verification methodology. This paper describes the innovation that was applied to tools and methodology in pre-silicon simulation, acceleration and post-silicon in order to verify transactional memory in the IBM POWER8 processor core.

To produce a marketable PowerPC microprocessor on a short development schedule, an appropriate balance was needed between a fully customized methodology and a standard cell approach. We compiled a single model of each logic partition separately for logic synthesis and for simulation. Synthesis transferred the model to a gate-level implementation and applied timing correction transforms to reach the users' timing assertions. Floor-planning and wiring was assisted by an automated tool. Billions of cycles were run in testing the implementation against the PowerPC architecture specification. Behaviorals were written and built into the model to test the chip as it might appear in a system configuration. Careful adherence to this methodology led to a successful first pass of silicon, leaving the second iteration for additional customer requests.>