If the rate of improvement in the performance of advanced silicon integrated circuits is to be sustained, new techniques for the measurement of electrical waveforms in operating circuits are needed. Critical factors dictating this requirement include the increased speed and complexity of circuits, the growing importance of faults that appear only during high-speed operation, and the use of flip-chip packaging technologies. Two recently developed all-optical methods for measuring the switching activity from the backside of a chip are described and compared. One is a passive approach based on the measurement of hot carrier luminescence emitted from the channel of a CMOS field-effect transistor (FET) during switching. The second uses a laser probe to sense the switching induced modulation of the silicon optical constants near an FET's source and drain.

SEMATECH has sponsored a "Test Method Evaluation" study to understand the trade-offs among the most common test methodologies used in the industry. This paper presents the results of the failure analysis portion of that project. The testing, reliability stressing, characterization, fault diagnosis and physical analysis results are presented for 25 devices including "IDDq-only" failures and "delay test-only" failures.

Technological advances such as flip-chip packaging, multiple hierarchical wiring planes, and ultra-high frequencies reduce the effectiveness of conventional diagnostic techniques. It has recently been demonstrated that light pulses emitted during circuit switching can be used to characterize the behaviour of integrated circuits. In this paper, a new method of circuit characterization using this technique is described. An example of the diagnosis of a timing failure caused by a resistive path to a single transistor is described.

SEMATECH has sponsored a "test method evaluation" study to understand the trade-offs among the most common test methodologies used in the industry. This paper presents the results of the failure analysis portion of that project. The testing, reliability stressing, characterization, fault diagnosis and physical analysis results are presented for 25 devices including "IDDq-only" failures and "delay test-only" failures.

This paper reviews the logic failure analysis process and the critical need for design-for-diagnostics. The use of flip-chip packaging will render hardware-based diagnostic techniques from the front side of the die obsolete, e.g., liquid crystal, electron beam testing, and photon emission microscopy. Two primary solutions are discussed: software-based diagnostic methods, e.g., scan, and the adaptation of hardware techniques to the backside of the die.