A physics-based multi-scale simulation methodology that analyses die stress variations generated by package fabrication is employed for warpage study. The methodology combines coordinate-dependent anisotropic effective properties extractor with finite element analysis (FEA) engine, and computes mechanical stress globally on a package-scale, as well as locally on a feature-scale. For the purpose of mechanical failure analysis in the early stage of a package design, the warpage measurements were used for the tool's calibration. The warpage measurements on printed circuit board (PCB), interposer and chiplet samples, during heating and subsequent cooling, were employed for calibrating the model parameters. The warpage simulation results on full package represented by PCB-interposer-chiplets stack demonstrate the overall good agreement with measurement profile. Performed study demonstrates that the developed electronic design automation (EDA) tool and methodology can be used for accurate warpage prediction in different types of IC stacks at early stage of package design.

A recently proposed methodology for electromigration (EM) assessment in on-chip power/ground grid of integrated circuits has been validated by means of measurements, performed on dedicated test grids. IR drop degradation in the grid is used for defining the EM failure criteria. Physics-based models are involved for simulation of EM-induced stress evolution in interconnect structures, void formation and evolution, resistance increase of the voided segments, and consequent re-distribution of electric current in the redundant grid paths. A grid-like test structure, fabricated with a 65 nm technology and consisting of two metal layers, allowed to calibrate the voiding models by tracking voltage evolution in all grid nodes in experiment and in simulation. Good fit of the measured and simulated time-to-failure (TTF) probability distribution was obtained in both cases of uniform and non-uniform temperature distribution across the grid. The second test grid was fabricated with a 28 nm technology, consisted of 4 metal layers, and contained power and ground nets connected to "quasi-cells" with poly-resistors, which were specially designed for operating at elevated temperatures ~350°C. The existing current distributions resulted in different behavior of EM-induced failures in these nets: a gradual voltage evolution in power net, and sharp changes in ground net were observed in experiment, and successfully reproduced in simulations.

The paper presents a multiscale simulation methodology and EDA tool that assesses the effect of thermal mechanical stresses arising after die assembly on chip performance. Existing non uniformities of feature geometries and composite nature of on-chip interconnect layers are addressed by developed methodology of the anisotropic effective thermomechanical material properties (EMP) that reduces complexity of FEA simulations and enhances the accuracy and performance. Physical nature of the calculated EMP makes it scalable with the simulation grid size, which enables resolution of stress/strain at different scales from package to device channel. With feature-scale resolution, the tool enables accurate calculation of stress components in the active region of each device, where the carrier mobility variation results in deviations of circuits performance. The tool's capability of back-annotation of the hierarchic Spice netlist with the stress values allows a user to perform circuit simulation in different stress environments, by placing the circuit block in different locations in the layout characterized by different distances from the stress sources, such as die edges and C4 bumps. Both schematic and post-layout netlists can be employed for finding optimal floorplan minimizing the stress impact at early design stages, as well as for the final design sign-off. Electrical measurements on a specially designed test-package were used for validation of the methodology. Good agreement between measured and simulated variations of device characteristics has been demonstrated.

A recently proposed theoretical methodology for the assessment of the electromigration (EM) induced IR-drop degradation in on-chip power/ground grids has been validated by means of measurements performed on real silicon. A voltage tapping technique was employed for the direct measurement of voltage variations at 162 nodes of the power net, stressed with 10 mA constant source current at an elevated temperature of 350 °C. A voltage drop between cathode and anode pads exceeding a specified threshold was considered as a failure. Times-to-failure (TTF) was measured on 19 packaged test grids and used for computing the mean TTF (MTTF). The EM-induced voltage degradation in this grid was also analyzed with an assessment methodology based on a simulation of stress evolution everywhere in the grid, resulting in a voiding in some of grid branches and corresponding resistance increase. A set of voiding compact models for different grid segments was developed and used in the simulations. The stochastic nature of the EM phenomenon was captured by introducing random distributions of atomic diffusivities and critical stresses across the grid and iterating them with Monte Carlo loops. A good fit between the measured voltage evolution kinetics at different grid nodes and that predicted by simulation, and the good agreement between measured and simulated failure distributions can be considered as the ever first experimental validation of this EM assessment methodology for on-chip power/ground (p/g) grids.

Electromigration (EM) degradation evolves slowly towards failure, over a period of years. This is why EM checking methods use effective current models to represent the underlying circuit workload, which are typically constant (DC) currents over time. However, ignoring all input current variations around the mean can be risky, because low-frequency input variations can have a significant impact on EM, resulting in shorter than expected lifetimes. With the use of dark silicon and multimodal chip operation, such low-frequency changes in workload are becoming increasingly common in modern designs. Ignoring these variations can lead to false positives and must be avoided. We tackle this by developing a stochastic effective current model for the input current waveforms that is easy for users to specify and which allows stochastic estimation of the impact of input variability on the lifetime. User-provided guidance on the expected durations of various modes of operation is used to provide input current variances, which are then propagated to provide variances around the stress waveforms in the metal network, which gives a more realistic estimate of the EM lifetime. Variance propagation can be expensive for large systems, but a novel simulation-like framework will be presented that allows efficient variance propagation for large interconnect trees. This has revealed that the variance can be highly significant. Even when the standard deviation of the inputs is small, at around 20--30% of the mean, we see a 30--40% drop in the lifetimes.

Electromigration (EM) is a major reliability concern in chip power grids in the wake of smaller feature sizes. EM degradation of grid metal lines can cause large voltage drops on the grid, leading to timing failures and logic errors. During the design process, modifications to the grid design may be required in order to protect from the risk of such EM-induced voltage drop failures. We consider this problem in light of recent efficient full-chip EM assessment techniques. We present a systematic approach that resizes the grid metal lines to meet a design target lifetime while requiring minimal increase in metal area of the grid.

Due to technology scaling, electromigration (EM) signoff has become increasingly difficult, mainly due to the use of inaccurate methods for EM assessment, such as the empirical Black's model. In this paper, we present a novel finite-differencebased approach for power grid EM checking using physics-based models, that can account for process, voltage, and temperature variations across the die. Our main contribution is to extend existing physical models for EM in metal branches to track EM degradation in multibranch interconnect trees. The extended model is represented as a homogeneous linear time invariant system. We also detect early failures and account for their impact on grid lifetime. We speed up our implementation by proposing a macromodeling-based filtering scheme and a predictor-based approach. Our results, for a number of IBM power grid benchmarks, confirm that Black's model is overly inaccurate. The lifetimes found using our physics-based approach are on average 2.75× longer than those based on a (calibrated) Black's model, as extended to handle mesh power grids. With a maximum runtime of 2.3 h among all the IBM benchmarks, our method appears to be suitable for very large scale integration circuits.

Electromigration (EM) is a key reliability concern in chip power/ ground (p/g) grids, which has been exacerbated by the high current levels and narrow metal lines in modern grids. EM checking is expensive due to the large sizes of modern p/g grids and is also inherently difficult due to the complex nature of the EM phenomenon. Traditional EM checking, based on empirical models, cannot capture the complexity of EM and better models are needed for accurate prediction. Thus, recent physics-based EM models have been proposed, which remain computationally expensive because they require solution of a system of partial differential equations (PDEs). In this paper, we propose a fast and scalable methodology for power grid EM verification, building on previous physics-based models. We first convert the PDE system to a succession of homogeneous linear time invariant (LTI) systems. Because these systems are found to be stiff, we numerically integrate them using optimized variable-step backward differentiation formulas (BDFs). Our method, for a number of IBM power grids and internal benchmarks, achieves an average speed-up of over 20x as compared to previously published work and has a runtime of only about 8 minutes for a 4 million node grid.

Electromigration (EM) has been considered to be the major reliability issue for current and future VLSI technologies. Current EM reliability analysis is overloaded by over-conservative and simplified EM models. Particularly the transient recovery effect in the EM-induced stress evolution kinetics has never been treated properly in all the existing analytical EM models. In this article, we propose a new physics-based dynamic compact EM model, which for the first time, can accurately predict the transient hydrostatic stress recovery effect in a confined metal wire. The new dynamic EM model is based on the direct analytical solution of one-dimensional Korhonen's equation with load driven by any unipolar or bipolar current waveforms under varying temperature. We show that the EM recovery effect can be quite significant even under unidirectional current loads. This healing process is sensitive to temperature, and higher temperatures lead to faster and more complete recovery. Such effect can be further exploited to significantly extend the lifetime of the interconnect wires if the chip current or power can be properly regulated and managed. As a result, the new dynamic EM model can be incorporated with existing dynamic thermal/power/reliability management and optimization approaches, devoted to reliability-aware optimization at multiple system levels (chip/server/rack/data centers). Presented results show that the proposed EM model agrees very well with the numerical analysis results under any time-varying current density and temperature profiles.

As technology advances, Time-Dependent Dielectric Breakdown (TDDB) has become one of the major reliability threats for Copper/low-k interconnects. This article presents a novel approach, techniques, and flow for the physics-based chip-scale assessment of backend low-k TDDB. In our work, the breakdown development is considered as the complementary combination of electric current path generation by means of diffusing metal ions and field-based hoping conductivity of the current carriers. It replaces the widely accepted across-layout electrostatic field based TDDB assessment. As a result, the model generated time-to-failure (TTF) is governed by kinetics of the electric current path generation, which is controlled by a time-dependent minimum metal ion concentration in the inter-metal dielectrics (IMD) gap-fill. Finite element analysis (FEA)-based simulations are used for populating the set of lookup tables, which provide a time to breakdown for any interconnect pattern with given geometries and voltages. A pattern-matching technique is used for extracting from the layout all patterns belonging to different classes of pattern shapes with different geometries, locations and electric loads. Experimental results obtained on a test chip show that upon the calibration the proposed flow provides a capability to evaluate chip-scale low-k TDDB reliability based on the calculated TTF and detect most leaking shapes in the layout.

Due to technology scaling, electromigration (EM) signoff has become increasingly difficult, mainly due to the use of inaccurate methods for EM assessment, such as the empirical Black's model. In this paper, we present a novel approach for EM checking using physics-based models of EM degradation, which effectively removes the inaccuracy, with negligible impact on run-time. Our main contribution is to extend the existing physical models for EMin metal branches to track the degradation in multi-branch interconnect trees. We also propose effective filtering and predictor-based schemes to speed up our implementation, with minimal impact on accuracy. Our results, for a number of IBM power grid benchmarks, confirm that Black's model is overly inaccurate. The lifetimes found using our physics-based approach are on average 3× longer than those based on a (calibrated) Black's model, such as currently used in industry. For the two largest IBM benchmarks (700K branches each), our runtime is comparable to that of the Black's based approach, requiring 3 hours for the largest grid.

Electromigration (EM) in very large scale integration (VLSI) interconnects has become one of the major reliability issues for current and future VLSI technologies. However, existing EM modeling and analysis techniques are mainly developed for a single wire. For practical VLSI chips, the elemental EM reliability unit called interconnect tree is a multibranch interconnect segment consisting of a continuously connected, highly conductive metal (Cu) lines terminated by diffusion barriers and located within the single level of metallization. The EM effects in those branches are not independent and have to be considered simultaneously. In this paper, we demonstrate, for the first time, a first principle-based analytical solution of this problem. We have derived the analytical expressions describing the hydrostatic stress evolution in several typical interconnect trees: 1) the straight-line three-terminal wires; 2) the T-shaped four-terminal wires; and 3) the cross-shaped five-terminal wires. The new approach solves the stress evolution in a multibranch tree by de-coupling the individual segments through the proper boundary conditions (BCs) accounting the interactions between different branches. By using Laplace transformation technique, analytical solutions are obtained for each type of the interconnect trees. The analytical solutions in terms of a set of auxiliary basis functions using the complementary error function agree well with the numerical analysis results. Our analysis further demonstrates that using the first two dominant basis functions can lead to 0.5% error, which is sufficient for practical EM analysis.

This paper presents a novel approach and techniques for physics-based electromigration (EM) assessment in power delivery networks of very large scale integration systems. An increase in the voltage drop above the threshold level, caused by EM-induced increase in resistances of the individual interconnect branches, is considered as a failure criterion. It replaces a currently employed conservative weakest branch criterion, which does not account an essential redundancy for current propagation existing in the power-ground (P/G) networks. EM-induced increase in the resistance of the individual grid branches is described in the approximation of the recently developed physics-based formalism for void nucleation and growth. An approach to calculation of the void nucleation times in the group of branches comprising the interconnect tree is implemented. As a result, P/G networks become time-varying linear networks. A developed technique for calculating the hydrostatic stress evolution inside a multibranch interconnect tree allows to avoid over optimistic prediction of the time-to-failure made with the Blech-Black analysis of individual branches of interconnect tree. Experimental results obtained on a number of International Business Machines Corporation benchmark circuits show that the proposed method will lead to less conservative estimation of the lifetime than the existing Black-Blech-based methods. It also reveals that the EM-induced failure is more likely to happen at the place where the hydrostatic stress predicted by the initial current density is large and is more likely to happen at longer times when the saturated void volume effect is taken into account.

Electromigration (EM) is projected to be the major reliability issue for current and future VLSI technologies. However, existing EM models and assessment techniques are mainly based on the constant current density and temperature. Such models will not work well at the system level as the current density (power) and temperature are changing with time due to different tasks (their loans) applied at run time. Existing EM approaches using average current density or temperature, however, will lead to significant errors as shown in this work. In this paper, we propose a new physics-based EM model considering time-varying temperature and current density, which reflects a more practical chip working conditions especially for multi-core and emerging 3D ICs. We study the impacts of the time-varying current densities and temperature profiles on EM-induced lifetime of a wire for both nucleation phase and growth phase. We propose a fast stress calculation method for given time-varying temperature and current densities for the nucleation phase. We further develop new formulae to compute the resistance changes in growth phase due to changing temperature and current densities. Experimental results show that the proposed method shows an excellent agreement with the detailed numerical analysis but with much improved efficiency.

Electromigration (EM) in VLSI interconnects has become one of the major reliability issues for current and future VLSI technologies. However, existing EM modeling and analysis techniques are mainly developed for a single wire. For practical VLSI chips, the interconnects such as clock and power grid networks typically consist of multi-branch metal segments representing a continuously connected, highly conductive metal (Cu) lines within one layer of metallization, terminating at diffusion barriers. The EM effects in those branches are not independent and they have to be considered simultaneously. In this paper, we demonstrate, for the first time, a first principle based analytic solution of this problem. We investigate the analytic expressions describing the hydrostatic stress evolution in several typical interconnect trees: the straight-line 3-terminal wires, the T-shaped 4-terminal wires and the cross-shaped 5-terminal wires. The new approach solves the stress evolution in a multi-branch tree by de-coupling the individual segments through the proper boundary conditions accounting the interactions between different branches. By using Laplace transformation technique, analytical solutions are obtained for each type of the interconnect trees. The analytical solutions in terms of a set of auxiliary basis functions using the complementary error function agree well with the numerical analysis results. Our analysis further demonstrates that using the first two dominant basis functions can lead to 0.5% error, which is sufficient for practical EM analysis.

A novel methodology for the post placement leakage reduction based on employment of the stress-enhanced filler (SEF) cells was developed. Desired reduction of sub-threshold leakage in test chip silicon was achieved by placement of SEF cells close to the most leaking devices. In the standard cell rows the “optimization zones”, representing portions of the row located between two consecutive fixed cells (clock cells, etc.), were defined. Mentor Graphics' stress assessment tool was used to find the optimal locations for SEF insertion inside each zone, providing the maximal increase of threshold voltage of the leakiest transistors. Measurements performed on the processed silicon test chip have confirmed the predicted leakage reduction of 10–15 percent while keeping same electrical performance.

This paper presents a novel approach and techniques for physics-based electromigration (EM) assessment in power delivery networks of VLSI systems. An increase in the voltage drop above the threshold level, caused by EM-induced increase in resistances of the individual interconnect segments, is considered as a failure criterion. It replaces a currently employed conservative weakest segment criterion, which does not account an essential redundancy for current propagation existing in the power-ground (p/g) networks. EM-induced increase in the resistance of the individual grid segments is described in the approximation of the recently developed physics-based formalism for void nucleation and growth. A statistical approach to calculation of the void nucleation times in the group of branches comprising the interconnect tree is implemented. As a result, p/g networks become time-varying linear networks. A developed technique for calculating the hydrostatic stress evolution inside a multi-branch interconnect tree allows to avoid over optimistic prediction of the time-to-failure (TTF) made with the Blech-Black analysis of individual branches of interconnect tree. Experimental results obtained on a number of IBM benchmark circuits validate the proposed methodology.

In this article, we propose a new lifetime task optimization technique for real-time embedded processors considering the electromigration-induced reliability. The new approach is based on a recently proposed physics-based electromigration (EM) model for more accurate EM assessment of a power grid network at the chip level. We apply the dynamic voltage and frequency scaling (DVFS) (by selecting the performance states or p-states of the tasks to manage the power) and thus the lifetime of the processor running different tasks over their periods. We consider both single-rate and multi-rate embedded systems with preemption. To model the mean-time-to-failure (MTTF) of a task for a given p-state, response surface modeling is applied. We then frame the reliability optimization problem as the continuous constrained nonlinear optimization problem in which the system EM-induced reliability is maximized subject to the timing constraints, which is further solved by simulated annealing method. Experimental results show that for low utilization systems, significant reliability improvement can be achieved with even smaller power consumption than existing reliability-ignore scheduling method. The proposed method can lead to near Pareto's front trade-off between the power/energy and the lifetime compared to the existing task scheduling method.

This paper presents a novel approach and techniques for electromigration (EM) assessment in power delivery networks. An increase in the voltage drop above the threshold level, caused by EM-induced increase in resistances of the individual interconnect segments, is considered as a failure criterion. This criterion replaces a currently employed conservative weakest segment criterion, which does not account an essential redundancy for current propagation existing in the power-ground (p/g) networks. EM-induced increase in the resistance of the individual grid segments is described in the approximation of the physics-based formalism for void nucleation and growth. A developed technique for calculating the hydrostatic stress distribution inside a multi branch interconnect tree allows to avoid over optimistic prediction of the time to failure made with the Blech-Black analysis of individual branches of interconnect segment. Experimental results obtained on the IBM benchmark circuit validate the proposed methods.

Modern CMOS technologies employ process-induced stress to improve carrier mobility and increase drive current. This stress has been shown to be strongly layout dependent; however there is a lack of physical models relating potential performance variation to critical layout parameters. This paper presents compact closed-form models that capture the layout dependence of mechanical stress induced in the device channel while considering all relevant sources of stress (STI, tensile/compressive nitride liners, and embedded SiGe). The models are calibrated using ring oscillator frequency data obtained from an experimental test chip to verify their accuracy. Results indicate that the models accurately capture the layout dependence of stress and carrier mobility for a variety of layout permutations and the root mean square error in the predicted ring oscillator frequency is less than 1% for the different layout experiments. These models can help drive layout optimization and timing/power analysis without the use of technology computer-aided design (TCAD) tools, which are slow and very limited in capacity.

Physically based simulations are used to predict an electromigration (EM)-induced void nucleation and growth in dual-inlaid copper interconnects. Incorporation of all important atom migration driving forces into the mass balance equation and its solution together with the solution of the coupled electromagnetics, heat transfer, and elasticity problems allows one to simulate EM-induced degradation in a variety of interconnect segments characterized by different dominant channels for mass transport. The existence of the weak interfaces between copper and diffusion barriers results in different EM-induced degradation pictures in aluminum and copper interconnects. The interface bonding strengths, significantly influencing the interface diffusivity and, consequently, the mass transport along interfaces in the case of copper interconnect, result in completely different degradation and failure pictures for the weak and strengthened copper/capping layer interfaces. Strengthening of the top interface of inlaid copper interconnect metal line is a promising way to prolong the EM lifetime. The correspondence between simulation results and experimental data indicates the applicability of the developed model for the optimization of the physical and electrical design rules. By varying the interconnect architecture, segment geometry, material properties, and some of the process parameters, users will be in a position to generate on-chip interconnect systems with high immunity to EM-induced failures.