Continuous-time (CT) Delta-Sigma (DS) ADCs are a popular choice for high resolution, medium bandwidth applications. A critical challenge is the excess-loop-delay (ELD) in the feedback path of the modulator, which causes performance degradation and instability. For free-running Delta-Sigma modulators (DSMs), performance can be fully recovered by adjusting the loop filter to restore the original noise transfer function (NTF) without ELD. For CT incremental Delta-Sigma (I-DS) ADCs, this has not been specifically investigated, but it is worth noting that the process of ELD compensation is slightly different. In this paper, we investigate the effect of ELD on I-DS ADCs and show that the performance cannot be fully recovered by NTF engineering as in the free-running case, but requires signal transfer function (STF) engineering as well. We also present solutions on how to engineer the STF and how to fully recover the performance even in the presence of ELD in CT I-DS ADCs.

The maximum stable amplitude (MSA) is an important characteristic of a Delta-Sigma modulator (DSM) for high resolution and power efficiency. In free-running DSMs it is known that the MSA usually corresponds to a similar value as the amplitude with the maximum signal-to-quantization-noise ratio (SQNR) and that it depends on several factors including: loopfilter architecture, loopfilter scaling and aggressiveness, internal quantizer bit-width, signal transfer function (STF) and input frequency. Commonly, incremental Delta-Sigma (I-DS) analog-to-digital converters (ADCs) are derived from free-running prototypes enhanced by a periodic reset, and the assumption is that the underlying characteristics remain the same. In contrast, we elaborate in this work that the MSA of I-DS ADCs doesn’t correspond to the amplitude with the maximum SQNR anymore and that this amplitude is not exclusively determined by the DSM, but also depends on the chosen reconstruction filter. Furthermore, the reasons for this interdependency of the reconstruction filter and the amplitude with maximum SQNR are highlighted and solutions to solve this problem are presented.

This work links Ring Oscillator (RO)-Physical Unclonable Function (PUF) specific design parameters with previously neglected area consumption per PUF bit. In prior art, the PUF specific design parameters such as number of ROs in a given RO collection that can be compared to one another and readout time are optimised in terms of e.g stability and/or power consumption. The influence of these design parameters on the effectively required area per bit remains overlooked, since optimization on area is mostly done simply by designing small ROs. This work establishes a relationship between the general design parameters and the area per bit for RO-PUFs. Using finite frequency readout resolution by means of a limited readout time, the RO-PUF is transformed into graph-theory and by finding a Minimum Spanning Tree (MST), the best possible yield of a given collection of ROs is determined. The given collection together with variable yield is then mapped to a certain demand on area per bit. An extensive yield analysis is performed which then is again mapped to a certain area per bit, leading to the proposed connection between readout time, amount of ROs in a collection and area per bit.The system-level analysis performed shows that a set of 8 ROs represents a sweet-spot in terms of area per bit as well as low read-out time.

This paper presents a power and area efficient digital communication interface for tiny distributed direct digitizing neural recorder ASICs on an ultra-flexible neural implant in a bus-like structure in order to realize a NeuroBus. The digital interface only requires 3 pins, does not need any preprogramming or trimming for address allocation and achieves a very low core area. The digital interface was implemented in a 1.2V 180nm CMOS technology and supports up to 100 spatially distributed neural recorder ASICs, consuming only$9\ \mu\mathrm{W}$of power per channel on a tiny area of$2380\ \mu\mathrm{m}^{2}$.

A well-known problem when using Physical Unclonable Functions for secret key generation and storage, is the instability of PUF responses due to environmental conditions like temperature variations. Using Ring Oscillator PUFs (RO-PUFs), a response bit is usually derived based on the comparison of a RO frequency with either a threshold or another RO frequency. Especially for multi-valued PUFs it is of importance to decrease RO frequency errors before digitization. Otherwise, these errors can result in a huge amount of bit-flips. To counteract environmental influence in the reproduction phase, we propose to map a frequency, which might be remeasured under a temperature condition different from initialization, closer to the initial frequency by using a method based on polynomial interpolation. This paper presents how such an approach can decrease errors in multi-valued responses and evaluates the error based on the used polynomial order and thus complexity.

This demo shows the automated characterization of Xilinx Zynq FPGAs on the Digilent Zybo with the help of a framework based on Partial Reconfiguration. Fine-granular measurements of the whole chip area reveals several aspects which have to be taken into account for PUF system design on these devices. In this demo, the visitor will get to know the general measurement approach and explanations about the provided results. With the help of a python based tool, the visitor can experience the workflow first-hand, generate their own measurements and use them to differentiate a single board from a set of multiple other boards. Further in-sight can be gained by analysis of the different statistical metrics and by combining measurements from multiple boards.

Physical Unclonable Functions utilize random variations from manufacturing to generate unpredictable, yet repeat-able fingerprints of devices for usage in a hardware cryptographic context. Most often, they are dedicated electrical circuits in integrated devices and thus occupy additional space while only few implementations exploiting already existing hardware. In this work, we analyze the possibility to extract hardware unique fingerprints from the distinct differential nonlinearities of analog-to-digital converters, which are present in almost every system. The transfer curves from measuring a large set of low-cost analog-to-digital converters with 12 bit resolution are analyzed regarding their quality as system fingerprints. Additional postprocessing methods are investigated for further improvement of the uniqueness metrics. The fingerprints are optimized to a perfect inter-hamming distance of 50% and close-to-maximum entropy. These improvements come at the cost of a reduced number of extracted bits, yet the minimum achieved number of 440 bits is sufficient for secret key generation. By thresholding and consequently avoiding unstable positions in the extracted bit-strings, the intra-hamming distance of unprocessed transfer curves could be reduced to less than 4%. Further measurements over a large temperature range shows that the error rate due to temperature drift never exceeds 13%.

Physical unclonable functions are integrated circuits well-known for their potential to replace dedicated secure storage of cryptographic keys. On FGPAs, ring-oscillators have received great attention as the most preferable implementation. Many measurement data sets have been published with large quantities of ring-oscillators on large quantities of chips. Yet, all these data sets are missing large quantities of readouts, which limits their usage for proving the efficiency of error correction algorithms. In this work, we present multiple different approaches of measurement control and readout extraction for external storage. We cover the full development process, beginning with slow extraction in early stages for maximum control up to final extraction with automated high-speed designs. Targeting a Zynq-7000 architecture, the final design extracts 3800 · 10000 readouts within 8.04 s, which relates to a data extraction rate of 36 Mbit/s. In comparison to an early stage design, which took 452.91s for the same measurement, a reduction in total run time of 98.2% was achieved.

Physical Unclonable Functions (PUFs) offer the possibility to produce unique fingerprints for integrated circuits. As raw PUF responses are affected by noise, some post-processing steps are necessary. We present a coding chain test framework for PUFs on Field Programmable Gate Arrays. The framework allows easy exchange, evaluation and comparison of different PUF implementations, coding algorithms and other chain modules. For a testing framework, the execution time of the evaluated algorithm is a bottleneck, since a huge amount of runs are supposed to be done. Hence, we additionally present a new type of Reed-Muller decoder hardware architecture using parallel modules to speed up the decoding process. The decoding time could be decreased by 95% in comparison to existing implementations at the cost of 41 times higher slice count.

The jitter sensitivity of continuous-time ΣΔ modulators is well known. It becomes an even more severe performance bottleneck in receiver applications, when out-of-band interferers are present together with colored phase noise. Bandpass ΣΔ modulators, as a competitive candidate for software-defined radios, are typically considered to be disadvantageous regarding jitter, and it can be shown that they are at least similarly affected by jitter as the mixer in a direct conversion receiver. In this paper, an analog interferer suppression technique is presented for bandpass ΣΔ modulators, which allows them to be more tolerant to interferer induced jitter error, thereby relaxing the overall clock phase noise requirements compared to other receiver architectures. The proposed technique is also combined with a previously published digital interferer suppression technique in order to provide suppression over a larger frequency range.

Like every integrated circuit, Arbiter-PUFs suffer from any ambience variations such as electrical noise, supply voltage variations and temperature fluctuations. In this work, we show that most bit-errors are related to small phase differences, for which noise dominates the readout bit value. We present an approach eliminating this influence by modifying the arbitration circuit part into an eye-opening oscillator. By utilizing the deadzone of two D-Flip-Flops, the decision about the response is delayed until the phase difference becomes significant enough. With this modification, we could increase the PUFs initial bit-error rate of 3.31% to almost zero. We also highlight important design choices for this solution, like the setup-time of the D-Flip-Flops and the minimum number of enforced oscillations.

In this paper, a comparison between three different current readouts for micro-potentiostats is presented: resistive transimpedance amplifier (R-TIA), capacitive transimpedance amplifier (C-TIA), and current-mode continuous-time sigma-delta modulator (Current-CTSDM). The comparison is carried out on the signal transfer function, the required amplifier gain-bandwidth (GBW), its input referred noise current, required area and power, and dynamic range. Each approach and its limitations are separately discussed. The three systems have been simulated using VerilogA models and the results are compared. It is shown that each system comes with its own limitations, however current-mode CTSDM are more beneficial due to their intrinsic digitization.

This paper shows a neural stimulator with 15V supply voltage combined with a neural low-noise amplifier (LNA) with a supply of ±1.65V around the common mode voltage (VCM) of 7.5V. In most implementations, the stimulator and recorder use the same supply domain, thus either leading to low voltage compliance (VC) for the stimulator or to high power consumption in the recorder. Obviously, a separation of both is the preferable choice, but comes with the challenge of effective protection of the low voltage (LV) sensitive input nodes of the recorder. A high voltage (HV) transistor used as a switch between the two parts enables different supply voltages for stimulator and recorder. Thus, a high current stimulator with high VC can be combined with a high efficient LV neural recorder. The presented implementation shows a stimulator with a maximum stimulation current of ±15mA with 5-bit resolution out of a 15V supply. The recording part consists of a LNA with a VCM of 7.5V and a supply voltage of ±1.65V around VCM - VDDLNA=9.15V and VSSLNA=5.85V. It consumes only 11.8μW and achieves an input referred root-mean-square (RMS) noise of 5.5μV in the frequency band of 1Hz to 100kHz. The design is implemented and simulated in a 0.18μm HV technology.

This paper considers the implementation of a continuous-time low-pass single-bit ΔΣ analog-digital converter (ADC) for radar applications. By taking advantage of the high transit frequency of a 0.25μm SiGe BiCMOS technology, the 3rd-order modulator operates at 1.92GHz and achieves 77.8dB SNDR within a bandwidth of 15MHz, when simulating the sensitive circuit parts on transistor level. Thanks to the inherent linearity of single-bit digital-analog converter (DAC), high linearity of 90dB spurious-free dynamic range (SFDR) can be achieved.

This paper presents the design of a 4 bit flash quantizer with an alternative low kickback, wide DC range input clocked core comparator. The quantizer is demonstrated within a third order continuous time (CT) ΔΣ modulator operating at an fSof 1GHz with an OSR of only 10. In using the proposed clocked core and output latch, a reduction in current consumption within all preamplifiers and resistor ladder can be established. The schematic based flash quantizer is designed in a 1.2V supply 90nm TMSC process, consumes an overall 1.47 mW, and has a decision time of 132 ps. As demonstrating within the exemplary ΔΣ modulator, a coefficient dependent SNDR of 69.8 dB within a 50MHz bandwidth is achieved. When comparing to other state of the art ΔΣ modulator quantizers it achieves one of the lowest power consumptions.

This paper presents an integrated neural stimulator with highly efficient power management solution, which is intended for a 1024 channel epi-retinal implant. The stimulator features an adaptive high quality LC matching network that compensates for the process variation in the resonance frequency of the inductive receiver and maximizes the link power transmission efficiency. Transcutaneous closed-loop power control is realized that enables optimum power transfer in spite of the coupling variation as well as the variation in the stimulation threshold/current. Finally, a programmable adaptive supply in the high voltage (HV) domain is implemented so to minimize the power dissipation during the active stimulation mode in terms of stimulus current/electrode impedance inconsistencies. The stimulator prototype is designed in AMS 0.35μm HV CMOS technology. In simulation, the power transmission efficiency of the telemetric link is improved by a factor of 2 by the resonance compensation circuits. In addition, automatic supply voltage adaptation of the stimulator from 13.1V to 8V has been achieved, resulting in maximum power saving of 40% for the implantable circuit.

In this paper we present a correlation based error estimation technique using a residual test signal for the linearization of multibit feedback DACs of lowpass and bandpass Delta-Sigma analog-to-digital converters. Using residual test signal insertion allows operating in background with only limited loss in peak performance during test. Opposed to dynamic element matching techniques, which are limited by the intrinsic nonlinearities in the feedback DAC, the presented method recovers the performance of highly nonlinear systems back to their ideal resolution.

A digital tuning approach for adjusting the frequency of a resonator in a bandpass integrated transmission-line based SDM (BP-ITLSDM) is presented. The resonators are tuned by switching the length of an integrated transmission line (ITL) instead of the conventional varactor tuning. It makes the compensation process for the finite gain bandwidth (GBW) of transconductances independent from the tuning process of the resonator. Additionally, the same resonator gain is achieved at different tuned frequencies. To reduce the effect of parasitics and digital control patterns, common mode signal switching (CMS) is employed. The simulations are performed for a 2.5GHz resonator using a 16-segmented switchable ITL with unit length of 430um. A frequency tuning range of 1.5GHz and a finite GBW compensating range up to half of the sampling rate 10GHz is achieved in a 0.25um BiCMOS SiGe technology.

This paper presents a Gm-C based field programmable analog array implemented in a 0.13 mum CMOS technology. It combines coarse adjustability via OTA and capacitor arrays, with fine tunability through floating gate bias current sources. It can instantiate almost arbitrarily complex continuous-time filters in a frequency range from 660 kHz to 135 MHz. Measurements show that filter coefficients can be tuned in steps of at least 1.5%, depending on filter type and bandwidth.

This work presents an approach based on Genetic Programming for the synthesis of continuous-time analog filters on a field-programmable analog array. A multi-objective algorithm is used to synthesize both the topology and parameter values of Gm-C filter structures to be instantiated on the FPAA based on a given filter specification. The presented algorithm is highly adapted to the underlying hardware platform, with the goal of making an efficient crossover of high-quality building blocks possible without biasing certain types of schemata. By manipulating of the program tree in the instantiation phase, it is assured that the resulting synthesized structure fits within the physical constraints of the underlying hardware platform.

This paper reports on a rapid-prototyping platform for high-frequency continuous-time analog filters to be used in communication front-ends. A field programmable analog array (FPAA) is presented, which implements a unique hexagonal topology of 55 tunable OTAs for reconfigurable instantiation of Gm-C filters in a 0.13 mum CMOS technology. It is the first analog array to achieve a bandwidth, which allows processing of intermediate frequencies used in communication systems. In addition to the intuitive manual mapping of analog filters to the chip structure, a genetic algorithm with hardware in the loop is used for automated synthesis of transfer functions.

This paper reports on a Field Programmable Analog Array (FPAA) for high-frequency continuous-time analog filters. A rapid-prototyping hardware is presented, which implements a unique hexagonal topology of 55 tunable OTAs for reconfigurable instantiation of Gm-C filters in a 0.13 mum CMOS technology. It is the first analog array to achieve a bandwidth, which allows processing of intermediate frequencies used in communication systems. The maximum power dissipation is 70 mW at 1.2 V supply. The intuitive chip structure allows direct mapping of Gm-C filter schematics with up to 7 independent nodes, immediate download to the hardware, and evaluation of the working prototype.

This work presents a novel approach to filter synthesis on a fieldprogrammable analog array (FPAA) architecture using a genetic algorithm (GA). First, a Matlab model of the FPAA is created and verified for compliance with transistor-level simulations of the FPAA. Using this model, differentfilter structures are built using an active-RC approach and evaluated. Secondly, a robust genetic algorithm is implemented in Matlab, which allows synthesis of analog filters on the given structure. Optimal parameters and operators of the genetic algorithm are identified by gradual adaptation andperformance evaluation, and the general feasibility is shown. Finally, the GA is used to overcome quantization-limitations of the FPAA structure and find configurations of filters, which would not have been achievable with traditional synthesis methods.

Field programmable analog filters (FPAAs) often lack the necessary bandwidth for high performance applications. This paper presents an FPAA based on Gm-C filters, which achieves routing without the use of transmission gates. Not only can the parameters of these filters be tuned, but also their order and structure. No additional capacitor is used for integration, only the MOS parasitic capacitances. A maximum bandwidth of 164 MHz has been achieved in simulations based on a 130 nm 1.2 V CMOS process. Distortion performance is high with a HD3 of less than -70dB for a 50mV@1MHz signal. Influences of parasitic capacitances are simulated using a test chip with 49 Gm-cells arranged in a hexagonal array.

A methodology for a field programmable analog array is presented, which is based on a hexagonal structure of tunable Gm- C stages and provides a reconfigurable front-end for continuous-time analog signal-processing. This paper describes the synthesis of a given filter transfer function onto hardware structures feasible on the array by using a genetic algorithm. The methodology and granularity of the analog array is not only designed to be usable for a genetic evolution but also to allow deduction and understanding of the evolved filters

A new methodology of field programmable analog arrays (FPAAs) is presented, which is particularly designed as hardware platform for the instantiation of continuous-time (CT) adaptable filters. The array topology consists of 17 digitally configurable analog blocks (CABs) connected through a hexagonal interconnect network. Each CAB is built of tunable G/sub m/-C integrators, which provide both routing and shaping of the analog signal and are the building blocks for high-speed continuous-time filters. Intelligent IO-buffers provide reconfiguration of the array with minimal disturbance of the continuous analog signal. The architecture is introduced and reviewed as hardware platform for any circuit that consists of the given number of G/sub m/-C cells and an exemplary instantiation of a 4th order biquad Butterworth filter is shown.