EDBT 2026 Demo / reviewers in the wild / expert
Robert Pasko
dblp:30/6412
· DBLP profile ↗
5ranked-venue papers
3as first author
0since 2021 · last 2005
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 88% Integrated circuit design · 12% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization › compiler optimization › redundancy elimination
common subexpression elimination |
0.0 | 1 | 1999 | A new algorithm for elimination of common subexpressions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999 |
Electronic design automation › logic synthesis › logic optimization
common subexpression elimination |
0.0 | 1 | 1999 | A new algorithm for elimination of common subexpressions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999 |
Electronic design automation
high-level synthesis |
0.0 | 1 | 1999 | A new algorithm for elimination of common subexpressions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1999 | A new algorithm for elimination of common subexpressions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999 |
Electronic design automation › high-level synthesis › constant multiplication
multiple constant multiplication |
0.0 | 1 | 1999 | A new algorithm for elimination of common subexpressions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999 |
Methods — techniques the papers use, named apart from their topics
add-shift operations · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2005 | Building heterogeneous plaftorm simulators in C++
Robert Pasko, Luc Rynders |
FDL | 1 |
| 2004 | High-Level Data-Access Analysis for Characterisation of (Sub)task-Level Parallelism in JavaabstractIn the era of future embedded systems the designer is confronted with multi-processor systems both for performance and energy reasons. Exploiting (sub)task-level parallelism is becoming crucial because the instruction-level parallelism alone is insufficient. The challenge is to build compiler tools that support the exploration of the task-level parallelism in the programs. To achieve this goal, we have designed an analysis framework to evaluate the potential parallelism from sequential object-oriented programs. Parallel-performance and data-access analysis are the crucial techniques for estimation of the transformation effects. We have implemented support for platform-independent data-access analysis and profiling of Java programs, which is an extension to our earlier parallel-performance analysis framework. The toolkit comprises automated design-time analysis for performance and data-access characterisation, program instrumentation, program-profiling support and post-processing analysis. We demonstrate the usability of our approach on a number of realistic Java applications. Richard Stahl, Robert Pasko, Francky Catthoor, Rudy Lauwereins, Diederik Verkest |
HIPS | 2 |
| 2003 | Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java
Richard Stahl, Robert Pasko, Luc Rijnders, Diederik Verkest, Serge Vernalde, Rudy Lauwereins, Francky Catthoor |
SCOPES | 2 |
| 2002 | Techniques to Evolve a C++ Based System Design LanguageabstractComplex systems-on-chip present one of the most challenging design problems. To meet this challenge, new design languages capable of modelling such heterogeneous, dynamic systems are needed. For implementation of such a language, the use of an object oriented C++ class library has proven to be a promising approach, since new classes dealing with design- and platform-specific problems can be added in a conceptual and seamlessly reusable way. This paper shows the development of such an extension aimed to provide a platform-independent high-level structured storage object through hiding of the low-level implementation details. It results in a completely virtualised, user-extendible component, suitable for use in heterogeneous systems. Robert Pasko, Serge Vernalde, Patrick Schaumont |
DATE | 1 |
| 1999 | A new algorithm for elimination of common subexpressionsabstractThe problem of an efficient hardware implementation of multiplications with one or more constants is encountered in many different digital signal-processing areas, such as image processing or digital filter optimization. In a more general form, this is a problem of common subexpression elimination, and as such it also occurs in compiler optimization and many high-level synthesis tasks. An efficient solution of this problem can yield significant improvements in important design parameters like implementation area or power consumption. In this paper, a new solution of the multiple constant multiplication problem based on the common subexpression elimination technique is presented. The performance of our method is demonstrated primarily on a finite-duration impulse response filter design. The idea is to implement a set of constant multiplications as a set of add-shift operations and to optimize these with respect to the common subexpressions afterwards. We show that the number of add/subtract operations can be reduced significantly this way. The applicability of the presented algorithm to the different high-level synthesis tasks is also indicated. Benchmarks demonstrating the algorithm's efficiency are included as well. Robert Pasko, Patrick Schaumont, Veerle Derudder, Serge Vernalde, Daniela Duracková |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |