Small businesses are the lifeblood of the U.S. economy, representing an astounding 99.9 percent of all businesses, creating two-thirds of net new jobs, and accounting for 44 percent of economic activity. Yet, 50 percent of small businesses go out of business in the first 5 years.

We present an analog-integrated circuit implementation of long short-term memory network, which is compatible with digital CMOS technology. We have used multiple-input floating gate MOSFETs as both the front-end to obtain converted analog signals and the differential pairs in proposed analog multipliers. Analog crossbar is built by the analog multiplier processing matrix and bitwise multiplications. We have shown that using current signals as internal transmission signals can largely reduce computation delay, compared to the digital implementation. We also have introduced analog blocks to work as activation functions for the algorithm. In the back-end of our design, we have used current comparators to achieve the output to be readable to external digital systems. We have designed the LSTM network with the matrix size of 16 × 16 in TSMC 180nm CMOS technology. The post-layout simulations show that the latency of one computing cycle is 1.19ns without memory, and power dissipation of the single analog LSTM computing core with 2 kilobytes SRAM at 200MHz is 460.3mW. The overhead of power dissipation due to SRAM access is 8.3%, in which the computing of each LSTM layer requires one computing cycle. The energy efficiency is 0.95TOP/s/W.

Multisocket computer systems are popular in workstations and servers. However, they suffer from the relatively low bandwidth of intersocket communication especially for massive parallel workloads that generate many intersocket requests for synchronizations and remote memory accesses. Intersocket traffic puts pressure on the underlying network connecting all processors with a limited bandwidth confined by pin resources. Given this constraint, we propose to dynamically increase the intersocket bandwidth by sacrificing off-chip memory bandwidth when systems have heavy intersocket communication but few off-chip memory accesses. Our design increases the physical bandwidth for intersocket communication via switching the function of pins from off-chip memory accesses to intersocket communication and can achieve an average performance speedup of 1.28 in geocentric mean for selected parallel multithreaded benchmarks.

The Applied Data Science (ADS) Invited Talks Track at KDD-2017 is a continuation of what has now become a "7-year tradition" at KDD conferences. This is the second year the track operates under the ADS name, an evolution from its origins at KDD-2011 as the "Industry Practice Expo". The KDD Conference on Knowledge Discovery and Data Mining (KDD) is the world's first, largest and best conference on Data Science, Data Mining, and Knowledge Discovery. It brings together a healthy mix of academic researchers, industry and government researchers, and practitioners from a wide range of institutions and fields. The primary focus on KDD is on peer-reviewed research contributions and the academic advancement of the field. This is an important goal and in fact the KDD conference is now recognized as the most competitive and prestigious forum for presenting high quality research results. KDD, being fundamentally an applied field, needs the strong representation of applied work of big impact. Over the years of running the conference we observed that our initial speaker-selection approach needed to be re-thought because of the important contributions made to the field outside traditional academic, industrial and government research laboratories. The result of this re-thinking was to create a forum that exposes important contributions to Data Science through Big Data Applications that address strategic problems. We wanted to effectively capture the rising importance of Data Science and Machine Learning especially in the Big Data environment where structured and unstructured data create special challenges, and of course present new opportunities. The goal of the Invited Talks Track is to curate contributions from leaders in our field who have made important contributions through the development of a system, the creation of a new and important business, or the development and market introduction of a product,. Some of these important contributions may never see an academic paper or detailed peer-reviewed paper written about them, yet they are of critical importance to our very applied field. To give you an idea of how rapidly growing this area is, and how this sector of our industry and promises to be highly disruptive across many industries, we cite a couple of articles out of a plethora of such coverage: According to IDC, the global revenues from Big Data and business will grow from $130.1 billion in 2016 to more than $203 billion in 2020, at a compound annual growth rate (CAGR) of 11.7% [1]. Furthermore, to quote from a Forbes article: "Data monetization" will become a major source of revenues, as the world will create 180 zettabytes of data (or 180 trillion gigabytes) in 2025, up from less than 10 zettabytes in 2015.? [2]

Off-chip memory bandwidth has been considered as one of the major limiting factors of processor performance, especially for multi-cores and many-cores. Conventional processor design allocates a large portion of off-chip pins to deliver power, leaving a small number of pins for processor signal communication. We observe that a processor requires much less power during memory intensive stages than is available. This is due to the fact that the frequencies of processor cores waiting for data to be fetched from offchip memories can be scaled down in order to save power without degrading performance. Motivated by this observation, we propose a dynamic pin switching technique to alleviate this bandwidth limitation. This technique is introduced to dynamically exploit surplus power delivery pins to provide extra bandwidth during memory intensive program phases, thereby significantly boosting performance. This work is extended to compare two approaches for increasing off chip bandwidths using switchable pins. Additionally, it shows significant performance improvements for memory intensive workloads on a memory subsystem using Phase Change Memory.

Electrothermal performance of multiwall carbon nanotubes (MWCNT)-based interconnects has been studied under the influence of self-heating. The interlayer insulator is a low-k (εr~ 2) dielectric. Various geometries have been studied for the normal operation and breakdown conditions. Electrothermal coupled equations have been solved iteratively by solving Fourier heat diffusion equation with a finite-element method. Within the relaxation time approximation, mean free path of the electron has been calculated under different scattering mechanisms. Landauer-Büttiker formalism resistance has been used for calculating electrical resistance. Breakdown voltages for varying MWCNT lengths have been calculated and found to be higher in MWCNT with a shorter length. Breakdown voltage varies from 8.2 to 12 V for inner diameters 10-40 nm of 5-μm interconnect length and 50-nm outer diameter. Breakdown voltage decreases with the increase in the length of interconnect. For a 5-μm long interconnect, the breakdown voltage is nearly 8 V whereas for the same diameter 1 μm long interconnect it is nearly 22 V. Breakdown current density depends on the geometry of the MWCNT and is estimated on the order of 108 A · cm-2.

This talk will cover recent innovations in large-scale machine learning and their applications on massive, real-world data sets at Verizon. These applications power new revenue generating products and services for the company and are hosted on a massive computing and storage platform known as Orion. We will discuss the architecture of Orion and the underlying algorithmic framework. We will also cover some of the real-world aspects of building a new organization dedicated to creating new product lines based on data science.

Performance of single walled carbon nanotube (SWCNT) bundle- based VLSI interconnects has been studied under the strong influence of scatterings induced by self-heating. Landauer Büttiker formalism along with Fourier heat transfer equation have been used to compute interconnect scattering parameters at various cross sectional areas of the interconnection. Cross sectional temperature calculation was performed using finite difference method considering temperature dependent thermal conductivity for primitive defect-less SWCNT bundles. Using the relaxation time approximation, we have studied scattering dynamics in calculating equivalent resistance. Electronic and thermal transport equations have been coupled and solved iteratively to get accurate estimation of temperatures and resistances. Study of scattering parameters shows low backscattering however significant transmission loss. Below 100GHz, for a 1µm long interconnect with 10 nm by10 nm cross sectional area shows S21 as high as 80dB. In terahertz regime transmission parameter S21 is in the range of few hundreds dB.

Off-chip memory bandwidth has been considered as one of the major limiting factors to processor performance, especially for multi-cores and many-cores. Conventional processor design allocates a large portion of off-chip pins to deliver power, leaving a small number of pins for processor signal communication. We observed that the processor requires much less power than that can be supplied during memory intensive stages. This is due to the fact that the frequencies of processor cores waiting for data to be fetched from off-chip memories can be scaled down in order to save power without degrading performance. In this work, motivated by this observation, we propose a dynamic pin switch technique to alleviate the bandwidth limitation issue. The technique is introduced to dynamically exploit the surplus pins for power delivery in the memory intensive phases and uses them to provide extra bandwidth for the program executions, thus significantly boosting the performance.

Data stream classification poses many challenges to the data mining community. In this paper, we address four such major challenges, namely, infinite length, concept-drift, concept-evolution, and feature-evolution. Since a data stream is theoretically infinite in length, it is impractical to store and use all the historical data for training. Concept-drift is a common phenomenon in data streams, which occurs as a result of changes in the underlying concepts. Concept-evolution occurs as a result of new classes evolving in the stream. Feature-evolution is a frequently occurring process in many streams, such as text streams, in which new features (i.e., words or phrases) appear as the stream progresses. Most existing data stream classification techniques address only the first two challenges, and ignore the latter two. In this paper, we propose an ensemble classification framework, where each classifier is equipped with a novel class detector, to address concept-drift and concept-evolution. To address feature-evolution, we propose a feature set homogenization technique. We also enhance the novel class detection module by making it more adaptive to the evolving stream, and enabling it to detect more than one novel class at a time. Comparison with state-of-the-art data stream classification techniques establishes the effectiveness of the proposed approach.

We have utilized our Multiwalled Carbon NanoTube (MWCNT) and Single-Walled Carbon NanoTube (SWCNT) bundle interconnects model in a widely used π model to study the performances of MWCNT and SWCNT bundle wire inductors and compared these with copper (Cu) inductors. The calculation results show that the Q-factors of Carbon NanoTube (CNT) wire (SWCNT bundle and MWCNT) inductors are higher than that of the Cu wire inductor. This is mainly due to much lower resistance of CNT and negligible skin effect in carbon nanotubes at higher frequencies. The application of CNT wire inductor in LC VCO is also studied and the Cadence/Spectre simulations show that VCOs with CNT bundle wire inductors have significantly improved performance such as the higher oscillation frequency and lower phase noise due to their smaller resistances and higher Q-factors. It is also noticed that CMOS LC VCO using a SWCNT bundle wire inductor has better performance when compared with the performance of LC VCO using the MWCNT wire inductor due to its lower resistance and higher Q-factor.

Phase noise is a critical factor that degrades the synchronization performance of a wireless communication receiver. Hot-carriers (HCs), found in the CMOS synchronization devices, are high-energy charge-carriers that can degrade the MOSFETs performance by damaging the internal device structure and lead to the phase noise increase therein. Such incremental phase noise can be related to the essential parameter, namely the MOSFET threshold voltage due to the HC effect, which is particularly evident in the short-channel MOSFET devices. In this letter, we analyze the impact of the phase noise arising from the HC effect on the wireless systems in terms of the bit-error-rate (BER) and the signal-to-interference-plus-noise ratio (SINR).

Phase noise is a critical factor that degrades the synchronization performance of a wireless communication receiver. Hot-carriers (HCs), found in the CMOS synchronization devices, are high-energy charge-carriers that can degrade the MOSFET's performance by damaging the internal structure and lead to an increase in the phase noise therein. The increase in the phase noise can be related to a critical parameter, the MOSFET threshold voltage. The HC effect is particularly evident in the short-channel MOSFET devices. In this paper, we analyze the impact of the phase noise arising from the HC effect on the single-carrier QAM systems in terms of the symbol-error-rate (SER) and the signal-to-interference-plus-noise ratio (SINR). We provide an exact analysis for the SER and SINR degradation for the QPSK systems in the presence of the phase noise, and verify our analytical results through computer simulations. In addition, we illustrate the performance degradation of the single-carrier 16-QAM and 64-QAM systems via Monte Carlo simulations. Through our analysis and simulations, we can show that the SER performance of the QPSK systems can deteriorate by two orders-of-magnitude at an SNR of 10 dB. Our analysis can help the design of receivers for single-carrier wireless systems built on short-channel MOSFET devices

Phase noise is the major cause of performance degradation in OFDM systems. Hot carriers (HCs), found in the CMOS-based synchronization circuits, are high-mobility charge carriers that affect the MOSFETs' stability by increasing the required operating threshold voltages. The HC effect manifests itself as the phase noise, which increases with the continued MOSFET operation and results in the performance degradation of the voltage-controlled oscillator (VCO) built on the MOSFETs. The MOSFET instability impacts on the OFDM system performance, by inducing intercarrier interference (ICI) and common phase error (CPE) on the subcarriers. In this paper, we evaluate the effect of ICI self-cancellation coding on the phase noise induced by the hot-carrier effect in OFDM systems.