EDBT 2026 Demo / reviewers in the wild / expert
Shoichi Shimizu
dblp:30/6721
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 2005
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 2 · 1 first-authorComputer networks · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Interconnection networks and networks-on-chip · 100% | |
| Computer networks
1 paper |
Internet architecture and protocols · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Interconnection networks and networks-on-chip › switch architecture
buffer design |
0.0 | 1 | 1991 | A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture · IEEE J. Sel. Areas Commun. 1991 |
Interconnection networks and networks-on-chip › router architecture
shared buffer design |
0.0 | 1 | 1991 | A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture · IEEE J. Sel. Areas Commun. 1991 |
Interconnection networks and networks-on-chip
switch architecture |
0.0 | 1 | 1991 | A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture · IEEE J. Sel. Areas Commun. 1991 |
Internet architecture and protocols › ATM networks
ATM switching |
0.0 | 1 | 1991 | A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture · IEEE J. Sel. Areas Commun. 1991 |
Methods — techniques the papers use, named apart from their topics
computer simulation · 0.0BiCMOS process · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2005 | Robust and Accurate Detection of Object Orientation and ID Without Color Segmentation
Shoichi Shimizu, Tomoyuki Nagahashi, Hironobu Fujiyoshi |
RoboCup | 1 |
| 2004 | A Method of Pseudo Stereo Vision from Images of Cameras Shutter Timing Adjusted
Hironobu Fujiyoshi, Shoichi Shimizu, Yasunori Nagasaka, Tomoichi Takahashi |
RoboCup | 2 |
| 1991 | A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer ArchitectureabstractThe authors present a one-chip scalable 8*8 shared buffer switch LSI which includes a 256-cell buffer. Speedup, flow control, and input slot rotation functions are provided in order to interconnect LSIs for scaling-up without degrading cell loss rates. Computer simulations show that these functions bring a satisfactory result and can make the cell loss- rate for a Clos three-stage network superior to that for the output buffer switch which includes the same amount of buffer space. A 0.8 mu m BiCMOS process is employed for this LSI. The total number of transistors is one million. This LSI has already been fabricated.> Yasuro Shobatake, Masahiko Motoyama, Emiko Shobatake, Takashi Kamitake, Shoichi Shimizu, Makoto Noda, Kenji Sakaue |
IEEE J. Sel. Areas Commun. | 5 |