We describe various design automation solutions for design migration to a dual-Vt process technology. We include the results of a Lagrangian Relaxation based tool, iSTATS, and a heuristic iterative optimization flow. Joint dual-Vt allocation and sizing reduces total power by 10+% compared with Vt allocation alone, and by 25+% compared with pure sizing methods. The heuristic flow requires 5x larger computation runtime than iSTATS due to its iterative nature.

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.

The use of low-threshold devices in low-voltage CMOS circuits leads to an exponential increase in the intrinsic leakage current. This threatens the effectiveness of I/sub DDQ/ testing for such low-voltage circuits because it is difficult to differentiate a defect-free circuit from defective circuits. Recently, several leakage control techniques have been proposed to reduce intrinsic leakage current, which may benefit I/sub DDQ/ testing. In this paper, we investigate the possibilities of applying different leakage control techniques to improve the fault coverage of I/sub DDQ/ testing. Results on a large number of benchmarks indicate that dual-threshold and vector control techniques can be very effective in improving fault coverage for I/sub DDQ/ testing for some circuits.

Power optimization has become an important issue for high performance designs. One way to achieve low-power and high performance circuits is to use dual-threshold voltages. High threshold transistors can be used in non-critical paths to reduce the leakage power, while lower threshold voltage is used for transistors in critical path(s) to achieve high performance. This paper proposes two low power and high performance CMOS design techniques-multiple channel length (M/sub L/CMOS) and multiple oxide thickness (M/sub ox/CMOS), based on dual V/sub th/, design technique. A comprehensive algorithm for selecting and assigning optimal transistor threshold voltage, channel length and oxide thickness is given. The simulation results on ISCAS benchmark circuits show that the total power consumption can be reduced by 21% for M/sub L/CMOS at low activity. Total power savings for M/sub ox/CMOS at low and high switching activities are about 42% and 24%, respectively.

Dual threshold technique has been proposed to reduce leakage power in low v oltage and low p o w er circuits by applying a high threshold voltage to some transistors in non-critical paths, while a low-threshold is used in critical path(s) to maintain the performance.Mixed-Vth (MVT) static CMOS design technique allows dierent thresholds within a logic gate, thereby increasing the number of high threshold transistors compared to the gate-level dual threshold technique.In this paper, a methodology for MVT CMOS circuit design is presented.Dierent MVT CMOS circuit schemes are considered and three algorithms are proposed for the transistorlevel threshold assignment under performance constraints.Results indicate that MVT CMOS design technique can provide about 20% more leakage reduction compared to the corresponding gate-level dual threshold technique.

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.

Reduction in leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transistors in critical paths. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby leakage current model which has been verified by IISPICE is used to estimate standby leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby leakage power savings for some ISCAS benchmarks can be more than 50%.

Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been verified by IISPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a by-product of this analysis, we can also determine the set of input vectors which can put the circuits in the low-power standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.