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Hyunchol Shin

dblp:30/7077 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 2010
0000-0003-1141-3428ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Physical-layer communications · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 100%

Topics — the 1 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › on-chip interconnect
wireless interconnect
0.012001
RF/wireless interconnect for inter- and intra-chip communications · Proc. IEEE 2001

Methods — techniques the papers use, named apart from their topics

multiple-access algorithms · 0.1microwave signal transmission · 0.1
YearPublicationVenuePosition
2010 On-the-fly speed and power scaling of an E-TSPC dual modulus prescaler using forward body bias in 0.25 μm CMOS
abstract
An extended true-single-phase-clock (E-TSPC) dual-modulus prescaler with a division ratio of 2 and 3 employs the forward body biasing (FBB) technique for achieving efficient on-the-fly speed and power control. The circuit is implemented in 0.25 urn CMOS. With the forward body bias voltage of 0.7 V applied to N- and P-FET's, the maximum operating frequency is improved by 80 and 87 % in the divide-by-2 and -3 modes, respectively, while the current dissipation is increased by 27 and 28 % As a result, the figure-of-merit of the prescaler is enhanced by 42 and 46 % for the divide-by-2 and 3 modes, respectively. The phase noise however does not show significant degradation at the FBB voltage less than 0.7 V. We believe that the FBB technique can be an efficient means of on-the-fly speed and power scaling in CMOS RF E-TSPC prescaler circuits.
Seungsoo Kim, Hyunchol Shin
ISCAS3
2001 RF/wireless interconnect for inter- and intra-chip communications
abstract
Recent studies showed that conventional approaches being used to solve problems imposed by hard-wired metal interconnects will eventually encounter fundamental limits and may impede the advance of future ultralarge-scale integrated circuits (ULSls). To surpass these fundamental limits, we introduce a novel RF/wireless interconnect concept for future inter- and intra-ULSI communications. Unlike the traditional "passive" metal interconnect, the "active" RF/wireless interconnect is based on low loss and dispersion-free microwave signal transmission, near-field capacitive coupling, and modem multiple-access algorithms. In this paper we address issues relevant to the signal channeling of the RF/wireless interconnect and discuss its advantages in speed, signal integrity, and channel reconfiguration. The electronic overhead required in the RF/wireless-interconnect system and its compatibility with the future ULSI and MCM (multi-chip-module) will be discussed as well.
Mau-Chung Frank Chang, Vwani P. Roychowdhury, Hyunchol Shin, Yongxi Qian
Proc. IEEE4
2000 Highly linear variable gain amplifiers with programmable temperature compensation for CDMA wireless applications
abstract
Highly linear and low power variable gain amplifiers (VGA's) with digitally programmable temperature compensation has been developed using a 15 GHz 0.5 /spl mu/m BiCMOS process for CDMA mobile phones. Receive-VGA (RxVGA) shows 135-dB gain control range, 4.95 dB noise figure at a maximum gain, and -1.35 dBm IIP3 at a minimum gain with current consumption of 8 mA. Transmit-VGA (TxVGA) shows an output P/sub 1 dB/ of 4.7 dBm with current consumption varying from 6 mA to 24 mA according to its gain. The temperature compensation has been achieved within /spl plusmn/0.2 dB variation over the entire temperature and gain range. In addition, for easy application of the VGA's for mobile handsets, a simple method is presented for a programmable temperature compensation. A two-bit digital input is used to modify the temperature compensation characteristics by 1.5 dB/1110/spl deg/C per a step.
Hyunchol Shin, Dong-Jin Keum, Jin-Sub Choi, Duck-Young Jung, Byeong-Ha Park
ISCAS1