This paper introduces a concept of provably detected defects that are identified through topology analysis and AMS verification database inquiry. The main purpose is to associate detected status to such defect without simulation, thereby reducing the size of defect simulation campaign. The proposed approach is a combination of fundamental and empirical rule-based set targeting relevant steps that are part of regular design sign-off. The feasibility is illustrated on an industrial product that is currently undergoing final stages of the tape-out, with the results complying to the current status of upcoming IEEE P2427 standard in development.

The paper proposes a method for identifying undetectable defects in mixed-signal circuits to exclude them from further consideration in defect campaigns. The method uses an equivalence checker to generate counterexamples or prove the undetectability of a defect.

This paper presents a powerful combination of Analog Mixed-Signal (AMS) verification in combination with emerging IEEE P1687.2 standard, capable of enabling automation of the large part of test pattern generation flow from the specification to Automatic Test Equipment (ATE). The inherent property of AMS verification to incorporate UVM based environment and a configuration with design modules described at arbitrary abstraction levels allows efficient pre-silicon test setup simulation. UVM also facilitates automated generation of STIL, used as the main vehicle to trigger various ATE instruments. The approach is piloted on a power amplifier product that contains BigA and not-so-small D portion. To the best of our knowledge, this is the first proposed self-containing flow that achieves test development reduction and provides guidance for test quality improvement while relying entirely on emerging and existing IEEE standards.

This paper presents a software package called fanTESTic to improve and speed up the test development process of designs with a significant portion of Analog and Mixed-signal circuits. The test development flow of the tool is based on pre-silicon validation through test setup simulation. The tool maps a number of standard test procedures typically executed at commercial tester platforms, into the simulation domain. Both the automatic testbench generator and postprocessing are integrated into the tool, compatible to any commercial Electronic Design Automation (EDA) environment. The approach is also applicable on embedded test instruments. To our best knowledge, fanTESTic is the first commercially available IEEE P1687.2-ready software kit.

This article describes an analog test bus infrastructure as a straightforward approach to grant the accessibility to embedded RF or Analog modules in core-based design. This DfT method increases the testability and provides debug/diagnosis facilities. The standardized analog test bus architecture is suited for an automated test development flow. In addition, the entire infrastructure is to a large extent reusable, through its design independence. This industrially innovative and practical approach has been applied to several products within our company, and two RF chips are chosen to illustrate its benefits.