Summary Financial markets change precipitously, and on‐demand pricing and risk models must be constantly recalibrated to reduce risk. However, certain classes of models are computationally intensive to robustly calibrate to intraday prices – stochastic volatility models being an archetypal example due to the non‐convexity of the objective function. In order to accelerate this procedure through parallel implementation, financial application developers are faced with an ever growing plethora of low‐level high‐performance computing frameworks such as Open Multi‐Processing, Open Computing Language, compute unified device architecture, or single instruction multiple data intrinsics, and forced to make a trade‐off between performance versus the portability, flexibility, and modularity of the code required to facilitate rapid in‐house model development and productionisation. This paper describes the acceleration of stochastic volatility model calibration on multi‐core CPUs and graphics processing units (GPUs) using the Xcelerit platform. By adopting a simple programming model, the Xcelerit platform enables the application developer to write sequential, high‐level C++ code, without concern for low‐level high‐performance computing frameworks. This platform provides the portability, flexibility, and modularity required by application developers. Speedups of up to 30x and 293x are respectively achieved on an Intel Xeon CPU and NVIDIA Tesla K40 GPU, compared with a sequential CPU implementation. The Xcelerit platform implementation is further shown to be equivalent in performance to a low‐level compute unified device architecture version. Overall, we are able to reduce the entire calibration process time of the sequential implementation from 6189 to 183.8 and 17.8 s on the CPU and GPU, respectively, without requiring the developer to reimplement in low‐level high‐performance computing frameworks. Copyright © 2015 John Wiley & Sons, Ltd.

Cognitive radio is a promising technology for fulfilling the spectrum and service requirements of future wireless communication systems. Real experimentation is a key factor for driving research forward. However, the experimentation testbeds available today are cumbersome to use, require detailed platform knowledge, and often lack high level design methods and tools. In this paper we propose a novel cognitive radio design technique, based on a high-level model which is implementation independent, supports design-time correctness checks, and clearly defines the underlying execution semantics. A radio designed using this technique can be synthesised to various real radio platforms automatically; detailed knowledge of the target platform is not required. The proposed technique therefore simplifies cognitive radio design and implementation significantly, allowing researchers to validate ideas in experiments without extensive engineering effort. One example target platform is proposed, comprising software and reconfigurable hardware. The design technique is demonstrated for this platform through the development of two realistic cognitive radio applications.

Adaptive systems are set to become more mainstream, as numerous practical applications in the communications domain emerge. FPGAs offer an ideal implementation platform, combining high performance with flexibility. While significant research has been undertaken in the area of FPGA partial reconfiguration, it has focussed primarily on low-level architecture-specific implementations. Building upon this previous work, we present a system model and software architecture for implementing runtime adaptive applications on FPGAs, separating the control and processing planes and abstracting away the details of hardware reconfiguration from the system designer. Hardware processing components appear as software components in the runtime system, enabling their inclusion in adaptive applications. We present an adaptive wireless application, demonstrating the use of the model and software architecture.

This paper identifies important features a cognitive radio framework should provide, namely a virtual architecture for hardware abstraction, an adaptive run-time system for managing cognition, and high level design tools for cognitive radio development. We evaluate a range of existing frameworks with respect to these, and propose a novel FPGA-based framework that provides all these features. By abstracting away the details of hardware reconfiguration, radio designers can implement FPGA-based cognitive nodes much as they would do for a software implementation. We apply the proposed framework to the design and implementation of a receiver node that works in two modes: discovery, where it uses spectrum sensing to find a radio transmission, and communication, in which it receives and demodulates the said transmission. We show how the whole design process does not require any hardware experience on behalf of the radio designer.