SRAM suffers from single event upset (SEU) and single event transient (SET) in harsh radiation environments. In this paper, a Penta Interlocking Dual Ports 14T (PIDP-14T) SRAM cell is proposed to improve cell stability. The PIDP-14T has the immunity of single node upset (SNU), multiple node upsets (MNU) and specific triple node upset (TNU). An inside-bit interleaving layout isolation method increases the distance of nearest sensitive nodes to 2.409 µm. Additionally, as SET in peripheral circuit results in half-select disturbance during the operation cycle, this paper introduced double module redundant (DMR) hardened decoding circuit to remove SET. The simulation results show that the cell can recover from special MNU of which the critical charge is almost 4 times of other cells, and the dual gate cell with DMR hardened decoding array are robust to write disturbance caused by SET.

The linear and nonlinear mismatches in time-interleaved analog-to-digital converter (TIADC) both severely degrade the system’s performance. Calibration techniques play a crucial role in restoring TIADC’s optimal performance. However, existing techniques have application limitations in nonlinear modeling and exhibit one-sidedness in error detection, leading to overfitting. This paper proposes a new background calibration for mixed linear and nonlinear errors. A unified model with wide applicability is presented to characterize mixed error generation based on the Taylor and the Volterra series. Then the errors are calibrated by a high-precision algorithm which addresses the issues of high dimensional optimization and overfitting problems simultaneously. The proposed technique is verified with simulations in MATLAB and experiments in a 16-bit 4-channel 260MS/s board-level prototype, improving the SFDR from 35.5 dB to 73.3 dB with a dual-tone input at 67.6 MHz and 119.6 MHz.

In recent years, natural, flexible, and contactless vision-based gesture recognition has received significant attention in human-computer interaction. However, employing convolutional neural networks (CNNs) for RGB or RGB-D gestures can result in excessive power consumption and poor energy efficiency, making them unsuitable for embedded systems. In this paper, we propose a lightweight sparse binarized neural network (sBNN) model for edge gesture recognition that achieves an accuracy of 89.43%-99.92% on four open-source gesture datasets with$\leq 20.26$million operations (MOP) and$\leq 15.83$-Kilobytes (KB) parameters. We find high channel-level sparsity in the activation maps of sBNN when edge gestures are used as inputs. The sparse activation maps have multiple identical activation vectors called sparse activation vectors (SAV), which lead to highly repeated calculations. In order to avoid this issue, we propose a two-stage value prediction approach to skip these calculations, achieving a speedup of 1.03x-1.83x. Moreover, to reduce on- chip memory, the compression technique is applied to the sparse activation maps, providing a compression rate of 1.72x-3.45x. Finally, we implement an energy-efficient sparse BNN accelerator (SBA) on an embedded field-programmable gate array (FPGA). The experimental results show that our SBA has a latency of 26.3-46.8-$\mu \text{s}$, a power consumption of 0.807 W, and an energy efficiency of 536.22-952.70-GOPS/W at 50-MHz frequency. Our SBA offers lower latency, lower power consumption, and higher energy efficiency than previous state-of-the-art gesture recognition accelerators.

Radiation Hardened by Design (RHBD) is one of the main measures for solving the soft error issue in digital circuits. However, a multi-objective optimization (MOO) problem obviously appears when utilizing the hardened counterparts to replace the original unreliable cells. This paper proposes a MOO framework based on Bayesian Optimization (BO) for balancing design metrics like area, Longest Path Delay (LPD)/power, and Soft Error Rate (SER) while hardening digital circuits, including combinational and sequential circuits. This framework comprises two phases: 1) data preprocessing and 2) multi-objective Bayesian optimization. The first phase makes this framework much more applicable for large-scale circuits through data dimensionality reduction. The second phase is characterized by utilizing a black-box approach to greatly promote the efficiency and accuracy of MOO. Experimental results on benchmark circuits demonstrate that the framework achieves a 1.34x improvement in accuracy, an 11.47x enhancement in efficiency, and a 0.77x reduction in SER, while exhibiting a 4.27x and 0.72x increase in area for combinational and sequential benchmark circuits, respectively, along with a 0.54x increase in LPD and a 1.25x increase in power for Triple Modular Redundancy (TMR) techniques.

With the scaling down of process, single event upset has been a critical issue for integrated circuits. It is much more likely to occur multiple-node upsets (MNUs) in CMOS ICs in advanced technology. However, the problem remains unsolved because of the lack of efficient methods. In this article, a non-redundant triple-node-upset(TNU)-tolerant latch with high reliability is proposed in 28 nm CMOS technology. The proposed latch named KOBE reduces the number of inner-sensitive nodes as well as the redundancy of the TNU-tolerant latch. In simulations, the proposed KOBE latch performs faster and lower power with higher reliability than most of the TNU-tolerant latches proposed before. The post-layout parasitic extracted simulations show that the proposed KOBE latch has an average improvement of 52.5% in a Power-Area-Delay Product (PADP) compared with the recently reported TNU-hardened latch at a supply voltage of 0.9 V, a working temperature of 27 °C. What’s more, by changing the working voltage and temperature, it is proved that the proposed KOBE latch has a better performance in a harsh environment. The results show that the proposed KOBE latch is of high beneficial efficiency and high reliability, thus can be used in safety-critical applications.

A self-biased voltage/current reference (VCR) generator provides bias for its embedded operational amplifier simply by itself. But during the power-up process, it is prone to be trapped into an undesired operating point called Trojan state (TS-UOP) that a conventional startup circuit (CSC) is unable to handle. This paper firstly simulates the power-up process of a self-biased VCR generator and discovers the dominant node that plays the leading role in the power-up convergence. Then, a dominant-node theory is proposed to find the dominant node based on the voltage-vertex directed dependency graph (DDG) and the Weight-Flow algorithm. In order to rescue the dominant node, a Monitoring-Rescue method is proposed as a general approach to enhanced startup circuits (ESCs) to eliminate TS-UOPs. An example of ESCs is designed in a 28-nm CMOS process. The measurement results verify that the ESC successfully helps the self-biased VCR generator converge to the desired operating point (DOP) regardless of the power-up ramping time range of$\mathrm {100~ \mu \text { s} }$to$\mathrm {100~ \text {m} \text { s} }$and the temperature range of$\mathrm {-45~ ^{\circ}C}$to$\mathrm {115~ ^{\circ}C}$.

This paper presents a novel fully synthesizable dynamic latched comparator with reduced kickback noise. A dynamic latched comparator is attractive to low power and high speed applications, but suffers from kickback noise. Although several kickback noise reduction techniques have been widely used, none of them can apply to synthesizable design flow. Inspired by the isolation technique, this paper employs OAI22 (4-input OR-AND-INVERT) gates to replace the NAND3 (3-input NAND) gates in the input stage of the conventional synthesizable dynamic latched comparator, so that the kickback noise can be significantly reduced due to the inherent isolation transistor in OAI22. Simulated in 28nm process, the proposed OAI22-based comparator achieves the maximum kickback noise of 8.63mV, compared with that of 46.16mV in the NAND3-based counterpart.

This paper presents a triple-output piezoelectric energy harvesting (PEH) system with parallel synchronized switch harvesting on capacitors (P-SSHC) rectifier based on shared capacitors. By analyzing the principle of the P-SSHC rectifier, this paper supports the rationality of using shared capacitors to construct the multi-voltage conversion ratio (VCR) switch capacitor (SC) DC-DC converters. In addition, the adoption of a parallel structure in the multi-output SC DC-DC converters reduces the cross-regulation. Simulation results show that the proposed system not only has good input power adaptability (1/3X,1X,2X) but can also provide triple voltage (0.5V, 1V, 2V) with less cross-regulation. The maximum output power is 14.4μW when peak-to-peak open circuit voltage is 1.7V.

This paper presents the first synthesis friendly dynamic amplifier (DA). The proposed fuzzy logic calibration makes its gain robust against process-voltage-temperature (PVT). In addition, the piecewise-linear linearization technique is also proposed for the fuzzy logic to tune the amplification phase, which compensates the time-domain non-linearity of the regeneration voltages, and accelerates the calibration convergence. The proposed DA is designed in 28-nm CMOS process, and verified by post-simulation results. It has a 16 × gain with -3.0%~3.6% deviations at TT corner once the calibration converges within 50 cycles.

A self-biased voltage/current reference (VCR) generator is simple, but suffers from some Trojan states surviving the conventional start-up process. After demonstrating this problem by simulation, this paper reveals the mechanism by identifying and analyzing all of the feedback loops that give rise to multiple Trojan states. Based on the theory, an enhanced start-up circuit is proposed that is capable of removing all Trojan states. Finally, the enhanced start-up circuit is embedded into a self-biased voltage reference generator, and designed in 28 nm CMOS process. The simulation results prove that the enhanced start-up circuit successfully eliminates all Trojan states in a wide temperature range for different process corners.

Conventional hardened cells are not robust enough to single event upset (SEU) in 28nm technology due to the scaling of the transistors. High soft error rate is caused by particle striking at cells and logic circuit in SRAM. This work proposes an SEU robust dual access 12T (DA-12T) SRAM with a radiation hardened crossbar-based peripheral circuit (CBPC). The proposed cell with 209% area penalty is more SEU robust than most cells. The CBPC can reduce the read failure rate of SRAMs. The new sense amplifier ensures the correct and rapid reading operation speed when suffering read disturbance. The experiment results show that the SEU cross-section of proposed cell is 60% of standard cell with dummy. Almost no read failure is observed in SRAM with CPBC when operational frequency exceeds 40MHz. Further investigation indicated that DA-12T cell and well isolation technique can reduce the read failure rate.

With the continuous scaling-down of transistors, the soft error issue of the combinational circuit becomes more serious. Triple Modular Redundancy (TMR) and Gate-Sizing (GS) are commonly used hardening methods for combinational circuits. However, the traditional TMR method is often applied at the module level, causing a large area overhead. Therefore, to explore the feasibility of refined and more general TMR, a General Efficient TMR (GE-TMR) method is proposed in this paper. Furthermore, since the hardening process is a multi-objective optimization problem, a Solution Distribution Optimized NSGA-II (SDON) algorithm is proposed. It features a trade-off between Soft Error Rate (SER), delay, and area. Based on the SDON, we systematically characterized and compared the three hardening methods, which are GE-TMR, GS, and MIX (a hybrid application of GE-TMR and GS). The experimental results show that GE-TMR can provide lower SER solutions (SER reduction >88%) than GS (SER reduction >85%) when the area overhead >200%. By combining GE-TMR and GS, in the interval of 100%81%) than the two hardening methods optimized separately (SER reduction of 64% and 80% for GE-TMR and GS, respectively).

Soft error is a major reliability concern in advanced technology nodes. Although mitigating Soft Error Rate (SER) will inevitably sacrifice area and power, few studies paid attention to optimization methods to explore trade-offs between area, power and SER. This paper proposes an optimization framework based on Bayesian approach for soft-error-tolerant circuit design. It comprises two steps:1) data preprocessing and 2) Bayesian optimization. In the preprocessing step, a strategy incorporating k-means algorithm and a novel sequencing algorithm is used to cluster Flip-Flops (FFs) with similar SER in order to reduce the dimensionality for the subsequent step. Bayesian Neural Network (BNN) is the applied surrogate model for acquiring the posterior distribution of three design metrics, while the Lower confidence bound (LCB) functions are employed as acquisition functions to select the next point based on BNN when optimizing. Finally, the non-dominated sorting genetic algorithm (NSGA-II) is used to search the Pareto Optimal Front (POF) solutions of three LCB functions. Experimental results demonstrate the proposed framework has a 1.4x improvement in accuracy and a 70% reduction in SER with acceptable increases in power and area.

This paper presents a methodology of the clock polarity inversion (CPI) technique to design integer and halfinteger frequency dividers. Based on a generalized structure of CPI dividers, the CPI-state allocation algorithms are derived for a CPI divider to achieve desired division ratio and duty cycle. The methodology is then demonstrated by a programmable CPI divider that is designed in a 65-nm CMOS process and verified by measurements.

This paper presents a synthesis friendly digital-like delta sigma (ΔΣ) analog-to-digital converter (ADC) based on voltage-controlled oscillator (VCO). The VCO is improved for low power and easiness of calibration. The proposed calibration technique establishes an extra feedback loop to prevent the center frequency of VCO from process variation. Taking the digital-like analog/mixed-signal (AMS) design flow, a 750MS/s ΔΣ ADC is designed in both 28nm and 65nm CMOS technologies with process variation tolerance and process migration verified by post-layout simulation. It is fabricated in 65nm CMOS technology and verified by measurement.

Conventional radiation-hardened cells of static random access memory (SRAM) are not robust enough in 28 nm technology, due to partial immunity of single-event upset (SEU) effect (Quatro-based cells) or insufficient critical charges in sensitive nodes (conventional stacked cells). The reduction of read noise margin (RNM) at the low supply voltage (VDD) confines these cells from low VDD applications. We propose a novel interleaving stacked-14T (ILS-14T) cell which prevents voltage transient from propagating to other redundancies. The ILS-14T cell can be resilient to both 0-1 and 1-0 upsets by injecting 12 mA in sensitive nodes. The critical charges of the ILS-14T cell are substantially larger than most other hardened cells at VDD from 0.3 to 0.9 V. The RNM of the ILS-14T cell is two times of most Quatro-based cells at 0.3 V VDD and larger than most cells at 0.6 and 0.9 V VDD. The area of occupation is 334% of the conventional 6T cell, which equals other 14T cells. The static-dynamic decoder array with 20%-40% area penalty and 116%-132% delay of rising edge, when compared with the conventional one, reduces the read failure rate by preventing single event transients (SETs) from propagating to unexpected word lines (WLs).

This brief proposes an ultralow-voltage four-read-port and two-write-port multiported register file with a novel architecture of read word-line sharing strategy for energy/area efficiency. Static read circuits and memory cells with nonminimum channel length are introduced to improve the ultralow-voltage performance. The chip of this register file is fabricated in 65-nm LP CMOS process and occupies the area of 0.019 mm$^{2}$ . Test results show that the minimum operation voltage is 320 mV with its corresponding max frequency 110 KHz. The minimum energy consumption is 0.94 pJ/cycle at the point of 400 mV, 850 KHz, corresponding to 0.15 fJ/port/bit/cycle after normalization. Compared with the state-of-the-art designs, it improves energy efficiency by 25% and saves the area by 58.7%.

A split-capacitor Vcm-based capacitor-switching scheme is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs) to reduce the capacitor-switching energy. By rearranging the structure and procedure of the capacitive array, the scheme can save the capacitor-switching energy by about 92% than the conventional scheme with better monotonicity. Meanwhile, a two-segment DC offset correction scheme for the comparator is also proposed to meet the speed and accuracy requirements. These techniques are utilized in the design of a 10b 70MS/s SAR ADC in 65nm 1P9M CMOS technology. Measurement results show a peak signal-to-noise-and-distortion ratio (SNDR) of 53.2dB, while consuming 960μW from 1.2V supply. The figure of merit (FoM) is 36.8fJ/Conversion-step and the total active area is 220×220μm2.