Demo Data from EDBT 2026 / reviewers in the wild / expert
Hitoshi Mizunuma
dblp:30/8358
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 2011
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 40% Energy-efficient computing · 40% Integrated circuit design · 20% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
3d integration |
0.1 | 1 | 2011 | Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011 |
Energy-efficient computing › thermal management
micro-channel cooling |
0.1 | 1 | 2011 | Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011 |
Electronic design automation
thermal analysis |
0.1 | 1 | 2011 | Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011 |
Electronic design automation › physical design › placement
thermal-aware placement |
0.1 | 1 | 2011 | Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011 |
Energy-efficient computing
thermal modeling |
0.1 | 1 | 2011 | Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011 |
Methods — techniques the papers use, named apart from their topics
thermal-wake function · 0.1finite volume simulation · 0.1channel merging · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2011 | Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel CoolingabstractIntegrated microchannel liquid-cooling technology is envisioned as a viable solution to alleviate an increasing thermal stress imposed by 3-D stacked ICs. Thermal modeling for microchannel cooling is challenging due to its complicated thermal-wake effect, a localized temperature wake phenomenon downstream of a heated source in the flow. This paper presents a fast and accurate thermal-wake aware thermal model for integrated microchannel 3-D ICs. A combination of the microchannel thermal-wake function and the channel merging technique achieves more than 3300× speedup with less than 5% error in comparison with a commercial numerical finite volume simulation tool. With the proposed model, we characterize thermal behaviors of microchannel-cooled 3-D ICs and compare them with the case of conventional air-cooled 3-D ICs. We also demonstrate thermal-aware placements using our thermal model. It shows that the proposed model can be used to reduce peak temperatures, which is considered important for 3-D IC designs. Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2009 | Thermal modeling for 3D-ICs with integrated microchannel coolingabstractIntegrated microchannel liquid-cooling technology is envisioned as a viable solution to alleviate an increasing thermal stress imposed by 3D stacked ICs. Thermal modeling for microchannel cooling is challenging due to its complicated thermal-wake effect, a localized temperature wake phenomenon downstream of a heated source in the flow. This paper presents a fast and accurate thermal-wake aware thermal model for integrated microchannel 3D ICs. Validation results show the proposed thermal model achieves more than 400x speed up and only 2.0% error in comparison with a commercial numerical simulation tool. We also demonstrate the use of the proposed thermal model for thermal optimization during the IC placement stage. We find that due to the thermal-wake effect, tiles are placed in the descending order of power magnitude along the flow direction. We also find that modeling thermal-wakes is critical for generating a thermal-aware placement for integrated microchannel-cooled 3D IC. It could result in up to 25°C peak temperature difference according to our experiments. Hitoshi Mizunuma, Chia-Lin Yang, Yi-Chang Lu |
ICCAD | 1 |