Modern wireless communication systems require efficient channel equalizer implementations. This paper explores the design space of reduced-state sequence estimation (RSSE). We show how the concept of pre-computation can be applied to greatly reduce computational complexity, such that efficient RSSE architectures can be derived. As a proof of concept, an RSSE was implemented in dedicated hardware, that achieves a 1.6 times higher hardware efficiency when compared to prior art.

In this paper, we investigate the impact of circuit misbehavior due to parametric variations and voltage scaling on the performance of wireless communication systems. Our study reveals the inherent error resilience of such systems and argues that sufficiently reliable operation can be maintained even in the presence of unreliable circuits and manufacturing defects. We further show how selective application of more robust circuit design techniques is sufficient to deal with high defect rates at low overhead and improve energy efficiency with negligible system performance degradation.

Trellis-based channel equalization for GSM/EDGE with 8PSK modulation requires pre-filtering to achieve high performance at acceptable complexity. Since corresponding implementation complexity grows with modulation order, the introduction of 16/32QAM in the latest 2G standard Evolved EDGE requires new solutions to preserve the low-cost attribute of EDGE-enabled devices. This paper describes a novel efficient pre-filter algorithm based on homomorphic filtering. The corresponding hardware implementation in 130 nm CMOS achieves a 5× improvement of area-timing (AT-)product when compared to prior art.

This paper presents a VLSI implementation of an MMSE successive interference cancellation multiuser detector (SIC-MUD) for the downlink of a TD-SCDMA system.Computation in the frequency domain, group-wise interference cancellation, and pre-computation of filter coefficients enable an efficient architecture suitable for mobile handsets.Our implementation in 0.13µm CMOS technology proves that the SIC-MUD is a viable solution for the TD-SCDMA downlink, providing a notable performance gain at a moderate increase in complexity compared to linear equalizers.

This paper addresses complexity issues at algorithmic and architectural level of digital baseband receiver ASIC design for GSM/GPRS/EDGE, in order to reduce power and die area as desired for cellular applications. A 2.5G multi-mode architecture is implemented in 0.13 μm CMOS technology occupying 1.0 mm2and dissipating only 1.3 mW in fastest EDGE data transmission mode.