In the digital age, cyber-threats are a growing concern for individuals, businesses, and governments alike. These threats can range from data breaches and identity theft to large-scale attacks on critical infrastructure. The consequences of such attacks can be severe, leading to financial losses, threats to national security, and the loss of lives. This paper presents a holistic approach to increase the security of critical infrastructures. For that, we propose an open, self-configurable, and AI-based automated cyber-defense platform that runs on specifically hardened devices and own hardware, can be deeply embedded in critical infrastructures and provides full visibility on network, endpoints, and software. In this paper, starting from a thorough analysis of related work, we describe the vision of our SOVEREIGN platform in the form of an architecture, discuss individual building blocks, and evaluate it qualitatively with respect to our requirements.

The security of embedded devices is very important today because critical infrastructures like medical devices, transportation, communication, and smart grids deploy them in large numbers. In all of these areas cybersecurity is the enabler for safety as failing or compromised devices threaten the life of people. Often, it is not feasible securing already deployed devices because of high costs, missing physical access, or defective hardware. Therefore, the next generation devices deployed in the future have to be more secure and more resilient to cyber attacks.This paper proposes a new approach to secure these next generation devices by using program optimized Application Specific Processors (ASPs) and employing an easy to integrate development flow for embedded developers. It evaluates the security improvement by analyzing the vulnerability of the approach against typical attack patterns.

In the past the security of building automation solely depended on the security of the devices inside or tightly connected to the building. In the last years more devices evolved using some kind of cloud service as a back-end or providers supplying some kind of device to the user. Also, the number of building automation systems connected to the Internet for management, control, and data storage increases every year. These developments cause the appearance of new threats on building automation. As Internet of Thing (IoT) and building automation intertwine more and more these threats are also valid for IoT installations. The paper presents new attack vectors and new threats using the threat model of Meyer et al.[1].

Synthesizing hardware from a Hardware Description Language (HDL) for Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) is very important today because many companies produce ASICs or use FPGAs for prototyping or High Performance Computing (HPC). Although, the synthesis, mapping and routing processes are well understood and good covered by research, some challenges in the operation of these processes exist, such as easy design space exploration, commercial license management, and different software version support which are not focus of research yet. This paper addresses these challenges by proposing the outsourcing of the whole hardware synthesis process into the cloud. A complete cloud-based synthesis service is presented consisting out of a command line client to deploy a synthesis process into the cloud, a remote web-service to schedule synthesis jobs within a cluster of servers or virtual machines, and a control webservice on each of these machines to start and stop the synthesis process. This service is evaluated against the standard local synthesis flow.

Security and privacy are very important assets within building and home automation because the System Control Unit (SCU) stores and processes a huge amount of data about the inhabitants or employees of the building. This data is necessary for managing the building and increasing the convenience of persons within. But this data can also be used to create a movement profile, monitor working times, and draw conclusions about people's health situation. Modern smart home implementations also control many actuators within the building including doors, windows, locks, and fire extinguisher. These increase security and safety, but unauthorized control can reduce the security and can even be harmful to persons. Therefore, identifying the different security and privacy threats is very important and helps system engineers and system managers to develop and deploy secure systems. This work presents an abstract model of a building automation system and some attack trees which simplify threat identification. Attack trees are common in secure software development and secure system deployment. An example smart home deployment is evaluated using the proposed model and attack trees to show the feasibility.

Partial runtime reconfiguration is a feature of modern Field Programmable Gate Arrays (FPGAs). It allows the reconfiguration of some parts of the FPGA, while other parts are still running and doing computations. The design flow to create a partially run-time reconfigurable system includes the partitioning of a FPGA into multiple collaborating Reconfigurable Modules (RMs), as part of the floor-planning design stage, and the development of an interconnection network. The latency of the chosen interconnection network determines the maximum clock speed the components inside the RMs can run at. The customary way of choosing design constraints to achieve the highest possible speed can lead to very long placement and routing times or even to an un-routable design. Eventually, the the Time To Market (TTM) of a product can be inreased. This paper proposes measuring the latencies of the interconnection network after a relaxed configuration phase. This is achieved by configuring two different kinds of components into the RMs and measure the round trip time of the network between them. Thus, the best placement of reconfigurable components, as well as the maximum clock rate of a given configuration can be calculated, and set without the need to rebuild the system. This enables the developer to place components into the RMs according to their clock speed requirements, without the need to reconfigure or rebuild the full system. This paper also presents some example measurements and an example placement of a small microcontroller.

In this paper we study Temporal Difference (TD) Learning with linear value function approximation. The classic TD algorithm is known to be unstable with linear function approximation and off-policy learning. Recently developed Gradient TD (GTD) algorithms have addressed this problem successfully. Despite their prominent properties of good scalability and convergence to correct solutions, they inherit the potential weakness of slow convergence as they are a stochastic gradient descent algorithm. Accelerated stochastic gradient descent algorithms have been developed to speed up convergence, while still keeping computational complexity low. In this work, we develop an accelerated stochastic gradient descent method for minimizing the Mean Squared Projected Bellman Error (MSPBE), and derive a bound for the Lipschitz constant of the gradient of the MSPBE, which plays a critical role in our proposed accelerated GTD algorithms. Our comprehensive numerical experiments demonstrate promising performance in solving the policy evaluation problem, in comparison to the GTD]algorithm family. In particular, accelerated TDC surpasses state-of-the-art algorithms.

Histology is the study of the structure of biological tissue using microscopy techniques. As digital imaging technology advances, high resolution microscopy of large tissue volumes is becoming feasible; however, new interactive tools are needed to explore and analyze the enormous datasets. In this paper we present a visualization framework that specifically targets interactive examination of arbitrarily large image stacks. Our framework is built upon two core techniques: display-aware processing and GPU-accelerated texture compression. With display-aware processing, only the currently visible image tiles are fetched and aligned on-the-fly, reducing memory bandwidth and minimizing the need for time-consuming global pre-processing. Our novel texture compression scheme for GPUs is tailored for quick browsing of image stacks. We evaluate the usability of our viewer for two histology applications: digital pathology and visualization of neural structure at nanoscale-resolution in serial electron micrographs.