This article presents a 52-mK noise-equivalent temperature difference (NETD) reference-cell-free wide temperature sensing range readout integrated circuit (ROIC) for a microbolometer thermal imager. The proposed ROIC utilizes a 15-bit hybrid analog-to-digital converter (ADC) that employs the current-mode folding integration (CMFI) technique for the coarse conversion and single-slope (SS) operation for the fine conversion. With the proposed coarse CMFI operation, the ROIC achieves a$300\times $larger conversion range and$300\times $higher conversion gain compared to the conventional nonfolding integration (NFI) technique. Moreover, due to the extended conversion range, the ROIC is able to cover the sensor’s PVT variations without any signal saturation. With the hybrid operation of CMFI and SS, the ROIC achieves a differential nonlinearity (DNL) and an integral nonlinearity (INL) of$\pm 0.04~^{\circ }$C and$\pm 0.12~^{\circ }$C, respectively. Furthermore, it achieves a wide temperature sensing range from$- 20~^{\circ }$C to$107~^{\circ }$C while considering ±15% chip-to-chip and ±3% cell-to-cell sensor variations.

Convolutional neural networks (CNNs) play a key role in deep learning applications. However, the large storage overheads and the substantial computational cost of CNNs are problematic in hardware accelerators. Computing-in-memory (CIM) architecture has demonstrated great potential to effectively compute large-scale matrix–vector multiplication. However, the intensive multiply and accumulation (MAC) operations executed on CIM macros remain bottlenecks for further improvement of energy efficiency and throughput. To reduce computational costs, model compression is a widely studied method to shrink the model size. For implementation in a static random access memory (SRAM) CIM–based accelerator, the model compression algorithm must consider the hardware limitations of CIM macros. In this study, a software and hardware co-design approach is proposed to design MARS, a SRAM-based CIM (SRAM CIM)-based CNN accelerator that can utilize multiple SRAM CIM macros as processing units and support a sparse CNN, and an SRAM CIM-aware model compression algorithm that considers a CIM architecture to reduce the number of network parameters. With the proposed hardware software co-designed method, MARS can reach over 700 and 400 FPS for CIFAR-10 and CIFAR-100, respectively. In addition, MARS achieves 52.3 and 88.2 TOPs/W in VGG16 and ResNet18, respectively.

This paper presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with reference voltage ripple suppression (RVRS) for wireless- powered implantable applications. Using two extra reference capacitive DACs and multiplexed four-input comparator, the reference voltage ripple on main DAC is mimicked and cancelled out during the conversion. By applying the RVRS technique with 2-bit ripple mimicking, the impact from unstable reference is effectively suppressed to be 1/4 (suppression ratio =3D 4) to release the reference voltage regulation requirement by 4 times and reduce power. The prototyped ADC was fabricated in 90nm CMOS technology with a core area of 0.088mm2. At 1V supply voltage and 3MS/s sampling rate, the implemented ADC achieves a SNDR of 62.69 dB with a corresponding ENOB of 10.12 bits. The resulting figure-of-merit (FoM) is 11.6 fJ/conversion-step.

This paper presents a monolithic optical encoder using CMOS image sensor (CIS) with background light cancellation. Both the absolute and incremental encoders are designed and fabricated on the same chip with dual photodiode arrays and the corresponding readout circuits. The absolute encoder is implemented using 42 columns of pixel with adjustable dual-threshold quantizer. The incremental encoder is implemented using the developed common-centroid interlacing (CCI) photodiode (PD) arrangement for the sensing of four quadrature sinusoidal signal with a 90° phase shift to each other. A fully-differential transimpedance amplifier (FDTIA) with current-mode subtraction (CMS) is proposed to achieve the common-mode signal rejection and background light cancellation. With the implemented CCI PD array, CMS FDTIA, programmable gain amplifiers (PGA), and 12-b SAR ADCs, the prototype achieves a SNR of 60dB, a total power of 10mW, and the maximum displacement error of 0.22μm. Compared to the reported work [5], it achieves a SNR improvement of 15dB, a 2× power reduction, and a 2× accuracy.

This paper presents a power-efficient 12-bit zero-crossing based (ZBC) successive-approximation register (SAR)-assisted two-stage pipeline analog-to-digital converter (ADC). The ZBC's error propagation of conventional multiple stage pipeline ADC is solved by using the proposed two-stage pipelined architecture with one residue amplification only. Moreover, to avoid the signal polarity dependent overshoot error of ZCB amplification, the adaptive level shifting (ALS) scheme is proposed to provide a constant polarity with a ×3 charge transfer speed improvement compared to the conventional approach. The prototyped ADC is fabricated in 40nm CMOS technology with core area of 0.019mm2. At 0.9V supply voltage and 40MS/s Sampling rate with 1MHZ input, the implemented ADC achieves a SNDR of 62.2dB with corresponding ENOB of 10.04 bits. The resulting figure-of-merit (FoM) is 5.6fJ/conversion-step.

Internet-of-things applications require high energy-efficient ADC. Several SAR ADCs have been reported [1-2] with comparatively low FoMs by reducing the switching energy of the power hungry capacitor array. This paper proposes a shifted monotonic switching (SMS) scheme to achieve an average switching energy of 63.75CV2 with a reduction of 75%, 72%, and 73% compared to monotonic switching (MS), sub-ranging (SR) procedure [1], and merge and split (MAS) switching [2] procedure, respectively. Proper redundancy design is also employed to tolerate the non-ideal effects including dynamic comparator offset, Vcm variation, and settling error.

This paper presents a low-voltage and power-efficient 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC). An input-range-adaptive (IRA) switching method is proposed to reduce the average switching power of capacitive-DAC (CDAC). By utilizing the comparator as a voltage-to-time converter (VTC) and implementation of time-domain quantizer, the input range is detected to efficiently eliminate the unnecessary CDAC switching power. A prototype ADC chip is fabricated in 90nm CMOS technology with an area of 0.038mm2, a Nyquist-rate input of 750kS/s, and a power consumption of 780nW at 0.4V supply. It achieves 9.0-ENOB and a resulting FoM of 1.94fJ/conversion-step.

This paper presents a 12-bit hybrid successive approximation register (SAR) analog-to-digital converter (ADC) composed of common-mode based switching procedure and time-to-digital converter (TDC). For high-resolution requirement, several issues including the signal-dependent coupling in bootstrapped sample-and-hold circuit and parasitic loading effect of voltage-to-time converter are addressed by proposed design schemes. TDC implemented in oscillation-type adjustable delay cell is proposed with smaller area. Calibration circuit is also implemented to compensate inter-stage offset mismatch and least-significant-bit level alignment. The prototype fabricated in TSMC 0.18μm CMOS technology achieves an effective number of bit (ENOB) of 10.5 bits at 1.2-V supply, 1MS/s, and 11.16μW, resulting in a figure of merit (FOM) of 7.65 fJ/conversion-step.

This paper presents an 8-bit asynchronous SAR ADC for CMOS image sensor applications in 130nm 1P4M technology. The proposed one-side merge-and-split switching effectively reduces the DAC switching energy because the reference voltage is halved. In addition, considering the bottom-plate parasitic capacitance, the proposed method can have better power efficiency compared to other methods. With 1.5V supply and Nyquist rate input, the prototype consumes 330μW at 16MS/s and achieves an ENOB of 7.21bit and a SFDR of 62.77dB, respectively. The resultant FoM is 139fJ/conv-step.

A 2.4-GHz industrial scientific and medical band binary frequency-shift-keying transmitter embedded in the Hypothesis, Odyssey, and Yield (HOY) wireless test system is presented and implemented, based on a 0.18-μm CMOS process. With the digitally controlled oscillator (DCO) using a stacked-LC tank, this transmitter occupies an area of only 0.1 mm2and has a measured phase noise of -111.8 dBc/Hz at a 500-kHz offset. The effects of stacking a spiral inductor over the other circuits are considered and examined using two DCO test chips. Both the antenna and the power amplifier are eliminated as a result of the short distance of transmission. By adopting an open-loop modulation architecture, a data rate of 10 Mb/s can be achieved. For a supply voltage of 1.5 V, the power consumption is only 9.2 mW and the emission output power measured at a distance of 1 cm is greater than -60 dBm.

This paper presents a 10b 500KS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) with input range prediction DAC switching technique for low power applications. The proposed input range prediction DAC switching technique narrows down the traditional try-and-error range of the input signal to prevent unnecessary DAC switching, and the average switching energy is 90% more efficient than the conventional approach. A prototype is fabricated in 0.18um CMOS technology. With a single supply of 1V, it achieves an ENOB, SNDR and FoM of 9.24b, 57.3dB, and 47fJ/Conversion-step at 500KS/s sampling rate, respectively.

the live demonstration shows the prototype of image recombination and processing system for one-dimensional multi-strip CMOS image sensors (CISs.) The proposed final system is discussed in the main paper, which takes advantage of the satellites' linear moving property to control the exposure time of CIS and provides the real-time ability to generate 11,200 × N high-resolution image for satellites' remote sensing applications. The prototype, which contains four strip CISs, is implemented to verify functionality and capability of real-time image acquisition and combination. The implementation result shows the proposed system, which demands four times larger throughput than the prototype, is feasible in a chip.

A 0.6V pulse frequency modulation (PFM) CMOS Image Sensor (CIS) array with in-pixel biphasic current pulse driver is presented in this paper. It achieves a photon-to-biphasic current conversion for biomedical applications like artificial 2-D vision recovery. The photon-to-biphasic-current conversion gain, the biphasic pulse width, polarity, and output rate are all tunable depends on applications and environments. A 32×32 pixel array with 30×30 um2pixel size has been designed and fabricated in 0.18um CMOS technology providing the fill factor of 24.5%. Measurement results show a 0.63Hz/lux conversion gain of PFM sensor within 25hz~5kHz output with power consumption as 2uW~55uW depends on illumination. The maximum driving capability of biphasic neural stimulation current pulse is ±20μA with a 10kΩ electrode model.

In this paper, a new 1 V rail-to-rail comparator is presented with low noise, high speed and low power consumption. We utilize current mirrors to overcome the kickback noise. A new adaptive power control (APC) technique is also proposed to minimize the power dissipation of the comparator. Moreover, it provides an optimized and stable power dissipation irrelative to process and bias variation. A prototype IV rail-to-rail SAR ADC for biomedical application has been implemented in 0.18 μm TSMC CMOS technology. It consumes 2.86 μW at 250kS/s and the figure of merit is 85.7 fJ/conversion-step. It shows that this work efficiently reduces 52% to 80% power consumption of the dynamic comparator at 500kS/s to 125kS/s.

A new linear current mode image sensor is proposed in this paper. The proposed circuit features high linearity, low power consumption, programmable multiple gain stages, wide input swing and correlated double sampling (CDS) technology. The signal swing of the linear current mode sensor is enhanced by the proposed multiple gain readout structure. A simple and accurate front-end programmable gain structure is proposed to improve the signal-to-noise ratio (SNR) with low power consumption. The function and performance has been verified by HSPICE simulation of 0.18 mum 3T sensor process.

A discussion of CMOS readout technologies for infrared (IR) imaging systems is presented. First, the description of various types of IR detector materials and structures is given. The advances of detector fabrication technology and microelectronics process technology have led to the development of large format array of IR imaging detectors. For such large IR FPAs which is the critical component of the advanced infrared imaging system, general requirement and specifications are described. To support a good interface between the FPA and downstream signal processing stage, both conventional and CMOS readout techniques are presented and discussed. Finally, future development directions including the smart focal plane concept are also introduced.