An asynchronous high-performance low-power 5-port network-on-chip (NoC) router is introduced. The proposed router integrates low-latency input buffers using a circular FIFO design, and a novel end-to-end credit-based virtual channel (VC) flow control for a replicated switch architecture. This asynchronous router is then compared to an AMD synchronous router, in a realistic advanced 14nm FinFET library. This is the first such comparison, to the best of our knowledge, using a real synchronous router baseline already fabricated in several commercial products. Initial post-synthesis pre-layout experiments show dominating results for the asynchronous router, when compared to the synchronous router. In particular, 55% less area and 28% latency improvement are observed for the asynchronous implementation. Also, 88% and 58% savings in idle and active power, respectively, are obtained.

Multicast communication (1-to-many) is common in parallel architectures and emerging areas such as neuromorphic computing. However, there is very limited research in supporting multicast in asynchronous NoCs. This paper proposes a new parallel multicast asynchronous NoC with 2D-mesh topology. To the best of our knowledge, this is the first general-purpose asynchronous NoC to support multicast in 2D meshes. A critical feature of this NoC is the use of a new continuous-time replication strategy, where the flits of a multicast packet are routed through the distinct outputs of the router according to each output's own rate, in parallel and in continuous time. This unique asynchronous continuous-time replication, not discretized to clock cycles, can handle subtle variations in network congestion and exploit "sub-cycle" differentials in operating speeds. A new continuous-time multi-way read (CMR) buffer is proposed to enable this replication strategy. Only a single CMR buffer is used per input port, with multiple independent read pointers, which are accessed by different outputs. For diverse multicast benchmarks, the new parallel multicast network achieved significant latency and throughput gains over a serial baseline. Moderate energy overhead was seen for one benchmark with a small multicast portion, but major reductions were achieved for higher amounts of multicast. Interestingly, consistent latency improvements were observed for unicast, in spite of the extra instrumentation. Experiments on isolated multicast packet transmissions also showed over an order-of-magnitude improvement in delivery time.

A new asynchronous arbitration node is introduced for use as a building block in an asynchronous interconnection network. The target network topology is a variant Mesh-of-Trees (MoT), combining a binary fan-out (i.e. routing) network and a binary fan-in (i.e. arbitration) network, which is becoming widely used for multi-core shared-memory interfaces. The two key features are: (i) each fan-in node can resolve its arbitration and pre-allocate the corresponding input channel, before the actual data arrives; and (ii) a lightweight shadow monitoring network fast forwards information as soon as data enters the network without synchronization to a fixed-rate clock, notifying each fan-in node on its path to enable the early arbitration. Simulations of the new arbitration node, using IBM 90nm technology and an ARM standard cell library, indicate latency reductions up to 54.4% over prior designs, while maintaining roughly comparable throughput. Network-level simulations were then performed on eight diverse synthetic benchmarks, comparing the new approach ("early arbitration") with two earlier alternative asynchronous MoT networks ("baseline" and "predictive"), using a mix of random and deterministic traffic. Considerable improvements in system latency were obtained on all benchmarks, ranging from 13.0% to 38.7%, with especially strong benefits for the two most adversarial benchmarks.

There is increasing interest in using m-of-n delay-insensitive codes for robust asynchronous global communication, to support the design of coding-efficient and low-power channels. However, a fundamental obstacle in using these codes has been complex and expensive hardware support. This paper addresses this issue, introducing and evaluating practical completion detector units for 2-of-n codes. Designs are proposed for both return-to-zero (RZ) and non-return-to-zero (NRZ) codes. The RZ designs build on prior work of Piestrak [14]; this paper proposes a small modification to their work to provide a fully timing-robust (i.e. quasi-delay insensitive, or QDI) version. The main contribution of the paper is an efficient completion for NRZ 2-of-n codes. Both detector architectures are modular and simple, composed of basic cells in a binary tree. Initial simulation results were performed on several implementations of a 2-of-9 detector using Cadence's Spectre environment, after mapping to a 90nm standard cell library. The new RZ detector has 35% area reduction and comparable delays and energy to the earlier Piestrak design, but unlike the latter, ensures robust QDI operation. The new NRZ detector is shown to have negligible stabilization time between successive codewords (0.05-0.19 ns) when compared to a recent alternative approach.