This paper introduces a cryogenic CMOS voltage-controlled oscillator (VCO) to generate the control signal for spintronic qubits in quantum computing applications. The proposed VCO utilizes a magnetically tuning trifilar transformer to achieve large output swing, low phase noise, and low power consumption. The tertiary coil of the trifilar transformer is applied to tune the primary and the secondary resonance frequency simultaneously to suppress the flicker noise up-conversion. In addition, switching the bias voltage of the center tap in the tertiary coil can achieve a wide tuning range. Fabricated in TSMC 40 nm CMOS process, the 28.3-to-31.4 GHz VCO consumes 5.4 mW under 0.6-V supply voltage, and achieves phase noise of –96.8 dBc/Hz at 1-MHz offset at room temperature (300K). When operating at 4K, the VCO operational frequency is slightly higher, from 29.1 GHz to 33.1 GHz, with a power consumption of 5.6 mW.

This work presents an energy-efficient on-chip resistive frequency-locked oscillator (RFLO) for achieving superb temperature and frequency stabilities. The resistive frequency-locked oscillator outperforms the power consumption and the temperature coefficient (TC) compared to the conventional relaxation oscillator. Frequency dividers are utilized in the feedback loop to reduce the reference current and clock power consumption. Moreover, switched-capacitor and switched-resistor techniques are both exploited to accomplish low area and low power consumption. This work was fabricated in TSMC$0.180\ \mu\mathrm{m}$process. The prototype operates at 200 kHz and achieves a 23.5 ppm/°C of TC across the temperature range from −40°C to 90°C and a line sensitivity of 0.44 %/V. Consuming 196 nW at 1 V supply voltage, it can reach a 0.98 pJ/cycle of energy efficiency.

A 423.5-450 MHz low-power OOK/FSK/QPSK wireless transmitter is proposed with multi-phase injection locking and frequency multiplication techniques. A low-frequency phase-rotation-based frequency synthesizer is employed to provide multichannel support and FSK modulation. The far-out phase noise caused by the quantization noise of the$\Delta \Sigma $modulator is filtered through a proposed N-path filter and two-stage injection-locked ring oscillators (ILROs). Phase modulation is achieved by changing the offset frequency between the oscillator free-running frequency and the injected frequency to control the steady-state phase offset of the injection-locked oscillator. Finally, a current mode class-D edge-combining power amplifier with high energy efficiency is used to achieve 5X frequency multiplication to generate the required carrier frequency. A prototype transmitter is fabricated in TSMC 90 nm CMOS process. It is shown that the device delivers an output power of −7 dBm with a power consumption of$870 \mu \text{W}$under a 0.75 V supply voltage and supports data rates of 40/5/80 Mbps under OOK/BFSK/QPSK modulation, respectively, achieving the energy efficiency of 11 pJ/bit and 23% global efficiency.

A resistive frequency-locked loop on-chip oscillator based on a double chopper stabilization technique is proposed for the improvement of frequency stability. The temperature-sensitive nonidealities, including the reference mismatch current and amplifier offset voltage, are suppressed by a double chopper stabilization technique. A prototype chip is implemented in a 180-nm CMOS process with an active area of 0.3 mm2. The measurement results show that the frequency-locked oscillator operating at 250 kHz achieves temperature stability of 27.1 ppm/°C and long-term stability of 2.73 ppm, with the power consumption of 293 nW. The mitigation of the low-frequency flicker noise results in a 16X improvement in the long-term stability of the RFLO compared to that with no chopper technique.

This article presents a high-sensitivity and high energy efficiency wake-up receiver (WuRx) based on an injection-locked oscillator (ILO) and an envelope detector to provide the capabilities of reliable demodulation for ON-OFF keying (OOK), binary frequency shift keying (BFSK), and differential binary phase shift keying (DBPSK) demodulation schemes. A 54- μW 433-MHz multimode WuRx is implemented in a 0.18- μm CMOS process. For a data rate of 200 kb/s and a bit error rate (BER) <; 0.1%, the receiver achieves sensitivities of -80/-78/-77 dBm under the OOK/BFSK/DBPSK demodulation schemes, respectively. Furthermore, incorporating an external loop antenna with a reception of an ILO, the receiver features a low-power mode of just 11 μW with a sensitivity of at least -71 dBm.

This work presents a resistive frequency-locked loop on-chip oscillator with a double chopper stabilization technique to improve the temperature stability and long-term stability. The negative feedback topology achieves both a low temperature coefficient (TC) and good energy efficiency. A prototype device is fabricated in 0.18-μm CMOS technology and exhibits a 24.7 ppm/°C temperature stability and 2.73 ppm long-term stability while consuming just 293 nW under an oscillation frequency of 250 kHz. The use of the double chopper stabilization technique effectively eliminates the TC-sensitive non-idealities, including the current mismatch and offset voltage of the amplifier. Moreover, the low-frequency flicker noise is also mitigated; resulting in a 16X improvement in the long-term stability.

An autonomous wireless transmitter with a piezoelectric energy harvester is presented for home automation and Internet of Things applications. The proposed ultra-low-power transmitter and high-efficiency energy harvester facilitates battery-less remote control with a small feature size. Each shot of the PZT generator produces an energy of more than 20 μJ Moreover, the piezoelectric harvester achieves a high conversion efficiency of up to 80% through the use of an inductor-switching circuit. Finally, the wireless transmitter realizes ultra-low power frequency synthesis by means of injection locking and frequency multiplication techniques. Operating at the 433 MHz ISM band, the transmitter delivers an output power of -12.9 dBm with a power consumption of 750 μW. A prototype device is fabricated with a size of 8.5 × 3.5 × 2.5 cm3.

This paper presents an ultra-low-power (ULP) ultra-wideband low noise amplifier (LNA) for sub-GHz applications. A current reuse negative shunt feedback technique is employed to provide additional design freedom to lower the power consumption of the gm-boost common gate (CG) LNA. Fabricated in 90 nm CMOS technology, the LNA achieves a peak voltage gain of 14.2 dB with a 3-dB bandwidth of 930 MHz, a noise figure of 6.5 dB and an IIP3 of -5.74 dBm, while consuming only 490 μW from a 1.2 V supply.

This paper presents an ultra-low-power wake-up receiver (WuRx) for use in the worldwide recognized 2.4 GHz ISM band. The WuRx features a fully-differential complementary current-reuse RF detector with an embedded impedance matching network. The proposed WuRx does not require power-hungry RF amplification and frequency down-conversion circuits, so the power consumption can be significantly reduced. The measurement results show that the proposed receiver achieves a sensitivity of -50 dBm and has a power consumption of just 4.5 μW in a 0.18-μm CMOS technology. Consequently, it provides a promising solution for a wide range of low-power wireless sensor network and wireless body area network applications.

Architectural schemes for low-power calibration of oversampled analog-to-digital (A/D) systems are presented. Conventional full-rate least-mean squares (LMS) calibration has two well-known limitations: slow convergence and increased computational complexity/power dissipation for higher adaptive filter orders and sampling frequencies. Half (fs/2) and quarter-rate (fs/4) LMS calibration for oversampled A/D decimators are used to reduce the computational complexity. Noble identities and polyphase decimation are used to implement these schemes to match digital noise-cancellation filters (NCF) to the corresponding transfer functions of an analog fourth-order cascade sigma-delta (ΣΔ) ADC. Energy savings up to 30% compared to conventional full-rate (fs) schemes are confirmed using an Altera Stratix II field programmable gate array (FPGA). The analog front-end comprises a switched-capacitor 2-2 cascade ΣΔ ADC implemented in 0.13 μm CMOS. Using differential-pair opamps with gains of only 22 db and an oversampling ratio OSR = 8, the ΣΔ ADC system achieves 11-bit accuracy over a 9.4 MHz bandwidth with SNR = 67 dB and SFDR = 75 dB.