Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Junshu Lin

dblp:300/1491 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
1since 2021 · last 2021
0000-0002-1838-7886ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 33% Energy-efficient computing · 33% Integrated circuit design · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › asynchronous circuit design
clockless logic
0.512021
A Data-Driven Asynchronous Neural Network Accelerator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021
Energy-efficient computing › energy-efficient architecture
energy-efficient accelerator
0.512021
A Data-Driven Asynchronous Neural Network Accelerator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.512021
A Data-Driven Asynchronous Neural Network Accelerator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021

Methods — techniques the papers use, named apart from their topics

quasi-delay-insensitive logic · 0.5bit-serial processing · 0.5asynchronous handshake protocol · 0.5
YearPublicationVenuePosition
2021 A Data-Driven Asynchronous Neural Network Accelerator
abstract
Deep neural networks (DNNs) are revolutionizing machine learning, with unprecedented accuracy on many AI tasks. Energy-efficient neural acceleration is crucial in broadening DNN applications in cloud and mobile end devices. However, power-hungry clock networks limit the energy-efficiency of DNN accelerators. In this work, we propose a novel DNN hardware accelerator, called the asynchronous neural network processor (AsNNP). At the heart of AsNNP is a scalable hierarchy matrix multiply unit, with bit-serial processing elements working in parallel. It replaces the global clock networks with asynchronous handshake protocols to realize the synchronization and communication between each part, minimizing the dynamic power. Meanwhile, a fine-grain asynchronous pipeline based on weak-conditioned half-buffer (WCHB) is introduced to pipe successive computations in a data-driven manner, i.e., once data arrives computation begins, maximizing the throughput. These techniques enable AsNNP to work in a fully data-driven asynchronous communication fashion with optimized energy-efficiency. The proposed accelerator is implemented with quasi-delay-insensitive (QDI) clockless logic family and evaluated in a 65 nm process. Compared with the synchronous baseline, simulation results show that AsNNP offers 2.2× higher equivalent frequency and 1.59× lower power. Compared with state-of-the-art DNN accelerators, AsNNP shows 1.17×-4.97× energy-efficiency improvement.
Shanlin Xiao, Weikun Liu, Junshu Lin, Zhiyi Yu
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3