Neuromorphic computing has emerged as a promising approach for energy-efficient artificial intelligence by emulating the spatiotemporal behavior of biological neural systems. This work presents a homeostatic plasticity-enabled CMOS neuron integrated with an SRAM-based synaptic architecture for event-driven spiking neural network (SNN) applications. The proposed design combines an 8T-SRAM synaptic framework with a mixed-signal leaky integrate-and-fire (LIF) neuron, enabling efficient spike accumulation without relying on power-intensive data converters. A programmable leak mechanism, governed by a digital homeostatic plasticity controller, dynamically adjusts neuron activity to maintain stable firing rates under varying input conditions. The circuits are implemented in TSMC 65 nm LP CMOS technology and evaluated using both circuit- and system-level simulations. Results demonstrate stable adaptive behavior and significant power efficiency improvements. The proposed architecture achieves an average power consumption of 117.5 μW, where the neuron consumes 58.12 μW and the synapse consumes 59.33 μW, providing 74% lower neuron power compared to state-of-the-art designs. Framework for evolutionary artificial general intelligence (FEAGI) based validation further demonstrates effectiveness in adaptive edge-intelligence applications such as cart-pole balancing.

Short-term plasticity (STP) is a synaptic modification process found in biological synapses that increases the computational power of the neuronal network. To implement plasticity rules, we use a memristor-based synapse due to its inherent plasticity. The synapse is designed to operate in the low resistance state (LRS) region using a current-controlled mechanism to account for the device non-idealities encountered at the high resistance state (HRS). In this work, we implement a mixed-signal STP circuit for this synapse design. The STP circuit uses a digital part to generate pulses to initiate the weight change, and an analog part to update the programming voltage. The STP functionality is verified using a 65nm CMOS process, and the performance metrics are reported. Results show that our circuit achieves a great performance in terms of area and power consumption.

Memristors provide a tempting solution for weighted synapse connections in neuromorphic computing due to their size and non-volatile nature. However, memristors are unreliable in the commonly used voltage-pulse-based programming approaches and require precisely shaped pulses to avoid programming failure. In this paper, we demonstrate a current-limiting-based solution that provides a more predictable analog memory behavior when reading and writing memristive synapses. With our proposed design READ current can be optimized by ~19x compared to the 1T1R design. Moreover, our proposed design saves ~9x energy compared to the 1T1R design. Our 3T1R design also shows promising write operation which is less affected by the process variation in MOSFETs and the inherent stochastic behavior of memristors. Memristors used for testing are hafnium oxide based and were fabricated in a 65 nm hybrid CMOS-memristor process. The proposed design also shows linear characteristics between the voltage applied and the resulting resistance for the writing operation. The simulation and measured data show similar patterns with respect to voltage pulse based programming and current compliance based programming. We further observed the impact of this behavior on neuromorphic-specific applications such as a spiking neural network.

In this paper, in an effort to emulate the properties of a biological neuron in silicon, we design a mixed-signal Integrate-And-Fire (IAF) neuron with two different approaches for the refractory period mechanism. The two approaches, one digital and one analog, have been designed to behave equivalently, except for the use of external programming signals. Neurons using both refractory blocks have been simulated using a 65nm CMOS process and their performances have been quantified in terms of area and power consumption. We find that although the analog refractory block can be made smaller than the digital counterpart by using a smaller capacitor, the area-power trade-off resulting from the use of a high programming current overshadows this advantage. The digital block is also found to perform better in terms of power consumption and programming precision.