Ferroelectric random access memory (FeRAM) is a promising candidate to further dynamic random access memory (DRAM) scaling. However, the design of the FeRAM bit cell is nontrivial as the ferroelectric device model is not well supported by EDA tools. Modern integrated circuit design heavily depends on circuit-level SPICE simulators that integrate compact device models through modified nodal analysis (MNA) representation. This paper presents a novel MNA-based SPICE simulation method for ferroelectric device models, targeted at the design space exploration of FeRAM bitcells. Furthermore, this paper provides a co-design procedure for FeRAM bitcells and sense amplifiers via a comprehensive case study.

Transformer-Based models have turned out to be very successful in many artificial intelligence (AI) tasks, outperforming traditional convolutional neural networks (CNNs), especially in the field of Natural Language Processing (NLP). Their success relies upon a self-attention mechanism which, when compared to CNNs, has a global rather than a local receptive domain. This article proposes an energy-efficient edge-device Transformer inference processor termed Smart Transformer Processing Element (STPE). Firstly, STPE sets up a Multi-Mode Indexing and Sparsity Scheme (MISS) for token association, and further reduces the computational load through in-situ computation; secondly, STPE exploits the Local Properties of Attention Mechanism (LPAM) to further reduce redundant and repetitive calculations in Transformer operations by means of a search band calculation and error correction mechanism; thirdly, STPE has designed a Quantization and Compression Parallel Method (QCPM) to improve the computing speed and hardware utilization under weak related (WR) token. Employing 28nm CMOS synthesis tools, the area of the proposed STPE processor is 7.33 mm2. Its peak energy efficiency is 84.15TOPS/W, which is 14.7 times higher than that of the H100 graphics processing unit (GPU) and 3.06 times higher than that of the most advanced Transformer processor.

Recently, Graph Neural Networks (GNNs) have shown great potential in terms of accuracy for problems that are well-described by graph representations, such as problems of path planning. However, implementing GNNs on mobile platforms is challenging as it requires a significant amount of computation and large memory. This article proposes a High-Performance Edge GNN Inference Processor termed GPE (GNN Processing Element). Firstly, GPE sets up Multi-Dimensional Indexing and Dynamic Pruning Schemes (MIDPS) for GNN networks, and achieves cross layer interconnection of multiple neighboring nodes via NOC (Network on Chip); secondly, GPE utilizes Graph Structure Adjacency Table Information (GSATI) of a GNN to further reduce redundant and repetitive calculations by means of repeated matching and difference transfer mechanisms; thirdly, GPE has a graph-based Multi Parallelism Simplification and Operation Method (MPSOM) to improve computing speed and hardware utilization under small data volumes. Using 28nm CMOS synthesis tools, the area of the proposed GPE processor is 5.37 square millimeters. Its peak energy efficiency is 21.5TOPS/W, which is 3.76 times higher than that of the H100 GPU (Graphics Processing Unit), while the energy consumption of GNN is 80.9% lower than the previous SOTA (State of Art) work.

Abstract Hafnium (Hf) oxide-based ferroelectric materials have emerged as a transformative platform for next-generation non-volatile memory and advanced computing technologies. This review comprehensively examines the development, challenges, and applications of HfO 2 ferroelectrics, emphasizing their CMOS compatibility, scalability, and robust polarization at nanoscale dimensions. Breakthroughs in doping strategies, stress engineering, and VO control have stabilized the metastable orthorhombic phase, enabling high-performance devices such as ferroelectric RAM (FeRAM), ferroelectric field-effect transistors (FeFETs), and ferroelectric tunnel junctions (FTJs). These devices offer ultrafast switching, low power consumption, and multi-level storage, driving innovations in neuromorphic computing, in-memory processing, and cryogenic systems; nonetheless, they face ongoing challenges in reliability, such as fatigue and imprint effects, and scalability at sub-5 nm technology nodes. Emerging frontiers, such as wurtzite-structured nitrides (e.g., AlScN) and antiferroelectric ZrO 2 -based systems, have garnered significant attention due to their exceptionally high remanent polarization and promising potential for enhanced endurance, respectively. Further addressing the reliability issues of these emerging ferroelectric materials and the challenges associated with large-scale integration processes through interdisciplinary efforts will unlock the full potential of ferroelectric technologies, positioning them as pivotal enablers of post-Moore computing architectures and sustainable AI-driven applications.