This work presents a novel configurable two-stage inverter-based ultra-low-power (ULP) OTA with digitally adjustable output stage for dynamic adjustments of gain-bandwidth product, (GBW) and average slew rate (${\mathbf {SR}}_{\mathbf {av}}$). This approach improves both the flexibility of the OTA compared to conventional DC-biased designs, providing a reliable solution for mitigating process, voltage, and temperature variations. The circuit is designed using standard cells in a 180-nm CMOS process and is then fully synthesizable. Experimental measurements are executed over process corners and voltage variations. The proposed OTA works at nominal 0.3-V power-supply voltage and consumes only 1.2 nW, while exhibiting 56-dB DC gain and 7.6-kHz maximum GBW with 5-pF capacitive load.

The paper introduces a four-stage operational transconductance amplifier (OTA) targeting ultra-low-power and ultra-low-voltage applications. The proposed circuit comprises a simple while effective compensation topology which entails a single Miller capacitor and an RC parallel block at the output of the third stage. Implemented in a standard CMOS 180-nm technology and powered at 0.3 V, this work uniquely benefits of power consumption reduction of a factor 39X-33,333X and a rail-to-rail dynamic range when compared with previous 4-stage OTAs. In addition, the proposed solution improves the state-of-the-art of high-gain multi-stage bulk-driven OTAs exhibiting a larger DC gain (>17.9 dB), a 1.9X improved gain-bandwidth product under higher maximum capacitive load (2.85X) and, hence, an increase of the F OMSof more than 4.4X.

This paper presents a 0.4-V bulk-driven two-stage operational transconductance amplifier (OTA) achieving an exceptionally high voltage gain exceeding 120 dB without requiring additional bias voltages. This is accomplished using a self-cascode composite transistor configuration. Common-mode and power-supply rejection ratios ( CMRR and PSRR, respectively) exceeding 90 dB are achieved through input stage optimization. An intrinsic current-buffer Miller compensation technique is also employed to enhance frequency performance. Compared to state-of-the-art designs, the proposed OTA exhibits superior performance in terms of gain-bandwidth trade-off, settling time, PSRR, and robustness against variations. This is demonstrated through extensive measurements across corner wafers and temperature within the range of -20∘C to 100∘C (unavailable in prior art).

This work proposes a very-low quiescent current corner-compensated analog LDO with reconfigurable topology for multiple output voltage values, and its pW-powered voltage reference. The design of the proposed LDO has been optimized for sub-1V for battery-less systems that exhibit an average power consumption from hundreds nW up to hundreds of μW. Measurement results on a 180nm standard CMOS technology prove the effectiveness of the design strategy and validate the working principle of the LDO. The proposed analog LDO can work with a supply voltage down to 0.55-0.6V, consuming only 15-nA of quiescent current and it shows 6.4x lower FoMt (7.5x for FoMtv) compared with similar prior art.

This work presents a 78.5-nA, 115-ppm/°C temperature coefficient, switched capacitor current reference for batteryless and US-powered implantable biomedical devices. It is also characterized by the presence of a trimming network that allows compensating the PVT variations. The circuit is designed in a 28-nm Bulk CMOS technology provided by TSMC and full post-layout characterization is provided. The proposed solution shows a 75.8-% power utilization, an overall power consumption of about 62 nW when operating under 0.6-V power supply the lowest area occupation compared with previous arts, making the circuit well suitable also for ultra-low power and sub-1V sensor nodes for the Internet-of-Things.